Microchip Technology Inc. ATSAML21G16A 2024.06.03 Atmel ATSAML21G16A device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, 48-pin package (refer to http://www.atmel.com/devices/SAML21G16A.aspx for more) CM0+ r0p1 little 2 false 8 32 AC Analog Comparators AC 0x0 0x0 0x40 registers n AC 23 COMPCTRL0 Comparator Control n 0x20 32 read-write n 0x0 0x0 ENABLE Enable 1 1 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0x0 MAJ3 3-bit majority function (2 of 3) 0x1 MAJ5 5-bit majority function (3 of 5) 0x2 HYST Hysteresis Level 20 2 HYSTSelect HYST50 50mV 0x0 HYST70 70mV 0x1 HYST90 90mV 0x2 HYST110 110mV 0x3 HYSTEN Hysteresis Enable 19 1 INTSEL Interrupt Selection 3 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0x0 RISING Interrupt on comparator output rising 0x1 FALLING Interrupt on comparator output falling 0x2 EOC Interrupt on end of comparison (single-shot mode only) 0x3 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 GND Ground 0x4 VSCALE VDD scaler 0x5 BANDGAP Internal bandgap voltage 0x6 DAC DAC output 0x7 MUXPOS Positive Input Mux Selection 12 3 MUXPOSSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 VSCALE VDD Scaler 0x4 OUT Output 28 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0x0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 0x1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 0x2 RUNSTDBY Run in Standby 6 1 SINGLE Single-Shot Mode 2 1 SPEED Speed Selection 16 2 SPEEDSelect LOW Low speed 0x0 MEDLOW Medium low speed 0x1 MEDHIGH Medium high speed 0x2 HIGH High speed 0x3 SWAP Swap Inputs and Invert 15 1 COMPCTRL1 Comparator Control n 0x34 32 read-write n 0x0 0x0 ENABLE Enable 1 1 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0x0 MAJ3 3-bit majority function (2 of 3) 0x1 MAJ5 5-bit majority function (3 of 5) 0x2 HYST Hysteresis Level 20 2 HYSTSelect HYST50 50mV 0x0 HYST70 70mV 0x1 HYST90 90mV 0x2 HYST110 110mV 0x3 HYSTEN Hysteresis Enable 19 1 INTSEL Interrupt Selection 3 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0x0 RISING Interrupt on comparator output rising 0x1 FALLING Interrupt on comparator output falling 0x2 EOC Interrupt on end of comparison (single-shot mode only) 0x3 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 GND Ground 0x4 VSCALE VDD scaler 0x5 BANDGAP Internal bandgap voltage 0x6 DAC DAC output 0x7 MUXPOS Positive Input Mux Selection 12 3 MUXPOSSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 VSCALE VDD Scaler 0x4 OUT Output 28 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0x0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 0x1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 0x2 RUNSTDBY Run in Standby 6 1 SINGLE Single-Shot Mode 2 1 SPEED Speed Selection 16 2 SPEEDSelect LOW Low speed 0x0 MEDLOW Medium low speed 0x1 MEDHIGH Medium high speed 0x2 HIGH High speed 0x3 SWAP Swap Inputs and Invert 15 1 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 SWRST Software Reset 0 1 write-only CTRLB Control B 0x1 8 write-only n 0x0 0x0 START0 Comparator 0 Start Comparison 0 1 START1 Comparator 1 Start Comparison 1 1 DBGCTRL Debug Control 0x9 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 EVCTRL Event Control 0x2 16 read-write n 0x0 0x0 COMPEI0 Comparator 0 Event Input Enable 8 1 COMPEI1 Comparator 1 Event Input Enable 9 1 COMPEO0 Comparator 0 Event Output Enable 0 1 COMPEO1 Comparator 1 Event Output Enable 1 1 INVEI0 Comparator 0 Input Event Invert Enable 12 1 INVEI1 Comparator 1 Input Event Invert Enable 13 1 WINEO0 Window 0 Event Output Enable 4 1 INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 WIN0 Window 0 Interrupt Enable 4 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 WIN0 Window 0 Interrupt Enable 4 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 COMP0 Comparator 0 0 1 COMP1 Comparator 1 1 1 WIN0 Window 0 4 1 SCALER0 Scaler n 0x18 8 read-write n 0x0 0x0 VALUE Scaler Value 0 6 SCALER1 Scaler n 0x25 8 read-write n 0x0 0x0 VALUE Scaler Value 0 6 STATUSA Status A 0x7 8 read-only n 0x0 0x0 STATE0 Comparator 0 Current State 0 1 read-only STATE1 Comparator 1 Current State 1 1 read-only WSTATE0 Window 0 Current State 4 2 read-only WSTATE0Select ABOVE Signal is above window 0x0 INSIDE Signal is inside window 0x1 BELOW Signal is below window 0x2 STATUSB Status B 0x8 8 read-only n 0x0 0x0 READY0 Comparator 0 Ready 0 1 read-only READY1 Comparator 1 Ready 1 1 read-only SYNCBUSY Synchronization Busy 0x20 32 read-only n 0x0 0x0 COMPCTRL0 COMPCTRL 0 Synchronization Busy 3 1 read-only COMPCTRL1 COMPCTRL 1 Synchronization Busy 4 1 read-only ENABLE Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only WINCTRL WINCTRL Synchronization Busy 2 1 read-only WINCTRL Window Control 0xA 8 read-write n 0x0 0x0 WEN0 Window 0 Mode Enable 0 1 WINTSEL0 Window 0 Interrupt Selection 1 2 WINTSEL0Select ABOVE Interrupt on signal above window 0x0 INSIDE Interrupt on signal inside window 0x1 BELOW Interrupt on signal below window 0x2 OUTSIDE Interrupt on signal outside window 0x3 ADC Analog Digital Converter ADC 0x0 0x0 0x2C registers n ADC 22 AVGCTRL Average Control 0xC 8 read-write n 0x0 0x0 ADJRES Adjusting Result / Division Coefficient 4 3 SAMPLENUM Number of Samples to be Collected 0 4 SAMPLENUMSelect 1 1 sample 0x0 2 2 samples 0x1 4 4 samples 0x2 8 8 samples 0x3 16 16 samples 0x4 32 32 samples 0x5 64 64 samples 0x6 128 128 samples 0x7 256 256 samples 0x8 512 512 samples 0x9 1024 1024 samples 0xa CALIB Calibration 0x2C 16 read-write n 0x0 0x0 BIASCOMP Bias Comparator Scaling 0 3 BIASREFBUF Bias Reference Buffer Scaling 8 3 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 CTRLB Control B 0x1 8 read-write n 0x0 0x0 PRESCALER Prescaler Configuration 0 3 PRESCALERSelect DIV2 Peripheral clock divided by 2 0x0 DIV4 Peripheral clock divided by 4 0x1 DIV8 Peripheral clock divided by 8 0x2 DIV16 Peripheral clock divided by 16 0x3 DIV32 Peripheral clock divided by 32 0x4 DIV64 Peripheral clock divided by 64 0x5 DIV128 Peripheral clock divided by 128 0x6 DIV256 Peripheral clock divided by 256 0x7 CTRLC Control C 0xA 16 read-write n 0x0 0x0 CORREN Digital Correction Logic Enable 3 1 DIFFMODE Differential Mode 0 1 FREERUN Free Running Mode 2 1 LEFTADJ Left-Adjusted Result 1 1 RESSEL Conversion Result Resolution 4 2 RESSELSelect 12BIT 12-bit result 0x0 16BIT For averaging mode output 0x1 10BIT 10-bit result 0x2 8BIT 8-bit result 0x3 WINMODE Window Monitor Mode 8 3 WINMODESelect DISABLE No window mode (default) 0x0 MODE1 RESULT > WINLT 0x1 MODE2 RESULT < WINUT 0x2 MODE3 WINLT < RESULT < WINUT 0x3 MODE4 !(WINLT < RESULT < WINUT) 0x4 DBGCTRL Debug Control 0x1C 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 EVCTRL Event Control 0x3 8 read-write n 0x0 0x0 FLUSHEI Flush Event Input Enable 0 1 FLUSHINV Flush Event Invert Enable 2 1 RESRDYEO Result Ready Event Out 4 1 STARTEI Start Conversion Event Input Enable 1 1 STARTINV Satrt Event Invert Enable 3 1 WINMONEO Window Monitor Event Out 5 1 GAINCORR Gain Correction 0x12 16 read-write n 0x0 0x0 GAINCORR Gain Correction Value 0 12 INPUTCTRL Input Control 0x8 16 read-write n 0x0 0x0 MUXNEG Negative Mux Input Selection 8 5 MUXNEGSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 AIN6 ADC AIN6 Pin 0x6 AIN7 ADC AIN7 Pin 0x7 MUXPOS Positive Mux Input Selection 0 5 MUXPOSSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 AIN16 ADC AIN16 Pin 0x10 AIN17 ADC AIN17 Pin 0x11 AIN18 ADC AIN18 Pin 0x12 AIN19 ADC AIN19 Pin 0x13 AIN20 ADC AIN20 Pin 0x14 AIN21 ADC AIN21 Pin 0x15 AIN22 ADC AIN22 Pin 0x16 AIN23 ADC AIN23 Pin 0x17 TEMP Temperature Sensor 0x18 BANDGAP Bandgap Voltage 0x19 SCALEDCOREVCC 1/4 Scaled Core Supply 0x1a SCALEDIOVCC 1/4 Scaled I/O Supply 0x1b DAC DAC Output 0x1c SCALEDVBAT 1/4 Scaled VBAT Supply 0x1d OPAMP01 OPAMP0 or OPAMP1 output 0x1e OPAMP2 OPAMP2 output 0x1f AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 AIN6 ADC AIN6 Pin 0x6 AIN7 ADC AIN7 Pin 0x7 AIN8 ADC AIN8 Pin 0x8 AIN9 ADC AIN9 Pin 0x9 AIN10 ADC AIN10 Pin 0xa AIN11 ADC AIN11 Pin 0xb AIN12 ADC AIN12 Pin 0xc AIN13 ADC AIN13 Pin 0xd AIN14 ADC AIN14 Pin 0xe AIN15 ADC AIN15 Pin 0xf INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Disable 1 1 RESRDY Result Ready Interrupt Disable 0 1 WINMON Window Monitor Interrupt Disable 2 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Enable 1 1 RESRDY Result Ready Interrupt Enable 0 1 WINMON Window Monitor Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Flag 1 1 RESRDY Result Ready Interrupt Flag 0 1 WINMON Window Monitor Interrupt Flag 2 1 OFFSETCORR Offset Correction 0x14 16 read-write n 0x0 0x0 OFFSETCORR Offset Correction Value 0 12 REFCTRL Reference Control 0x2 8 read-write n 0x0 0x0 REFCOMP Reference Buffer Offset Compensation Enable 7 1 REFSEL Reference Selection 0 4 REFSELSelect INTREF Internal Bandgap Reference 0x0 INTVCC0 1/1.6 VDDANA 0x1 INTVCC1 1/2 VDDANA 0x2 AREFA External Reference 0x3 AREFB External Reference 0x4 INTVCC2 VCCANA 0x5 RESULT Result 0x24 16 read-only n 0x0 0x0 RESULT Result Value 0 16 read-only SAMPCTRL Sample Time Control 0xD 8 read-write n 0x0 0x0 OFFCOMP Comparator Offset Compensation Enable 7 1 SAMPLEN Sampling Time Length 0 6 SEQCTRL Sequence Control 0x28 32 read-write n 0x0 0x0 SEQEN Enable Positive Input in the Sequence 0 32 SEQSTATUS Sequence Status 0x7 8 read-only n 0x0 0x0 SEQBUSY Sequence Busy 7 1 read-only SEQSTATE Sequence State 0 5 read-only SWTRIG Software Trigger 0x18 8 read-write n 0x0 0x0 FLUSH ADC Flush 0 1 START Start ADC Conversion 1 1 SYNCBUSY Synchronization Busy 0x20 16 read-only n 0x0 0x0 AVGCTRL AVGCTRL Synchronization Busy 4 1 read-only CTRLC CTRLC Synchronization Busy 3 1 read-only ENABLE ENABLE Synchronization Busy 1 1 read-only GAINCORR GAINCORR Synchronization Busy 8 1 read-only INPUTCTRL INPUTCTRL Synchronization Busy 2 1 read-only OFFSETCORR OFFSETCTRL Synchronization Busy 9 1 read-only SAMPCTRL SAMPCTRL Synchronization Busy 5 1 read-only SWRST SWRST Synchronization Busy 0 1 read-only SWTRIG SWTRG Synchronization Busy 10 1 read-only WINLT WINLT Synchronization Busy 6 1 read-only WINUT WINUT Synchronization Busy 7 1 read-only WINLT Window Monitor Lower Threshold 0xE 16 read-write n 0x0 0x0 WINLT Window Lower Threshold 0 16 WINUT Window Monitor Upper Threshold 0x10 16 read-write n 0x0 0x0 WINUT Window Upper Threshold 0 16 AES Advanced Encryption Standard AES 0x0 0x0 0x100 registers n AES 26 CIPLEN Cipher Length 0x80 32 read-write n 0x0 0x0 CTRLA Control A 0x0 32 read-write n 0x0 0x0 AESMODE AES Modes of operation 2 3 CFBS CFB Types 5 3 CIPHER Cipher mode 10 1 CTYPE Counter measure types 16 4 ENABLE Enable 1 1 KEYGEN Last key generation 13 1 KEYSIZE Keysize 8 2 LOD LOD Enable 12 1 STARTMODE Start mode 11 1 SWRST Software Reset 0 1 XORKEY Xor Key operation 14 1 CTRLB Control B 0x4 8 read-write n 0x0 0x0 EOM End of message 2 1 GFMUL GF Multiplication 3 1 NEWMSG New message 1 1 START Manual Start 0 1 DATABUFPTR Data buffer pointer 0x8 8 read-write n 0x0 0x0 INDATAPTR Input Data Pointer 0 2 DBGCTRL Debug control 0x9 8 write-only n 0x0 0x0 DBGRUN Debug Run 0 1 GHASH0 Galois Hash n 0xD8 32 read-write n 0x0 0x0 GHASH1 Galois Hash n 0x148 32 read-write n 0x0 0x0 GHASH2 Galois Hash n 0x1BC 32 read-write n 0x0 0x0 GHASH3 Galois Hash n 0x234 32 read-write n 0x0 0x0 HASHKEY0 Hash key n 0xB8 32 read-write n 0x0 0x0 HASHKEY1 Hash key n 0x118 32 read-write n 0x0 0x0 HASHKEY2 Hash key n 0x17C 32 read-write n 0x0 0x0 HASHKEY3 Hash key n 0x1E4 32 read-write n 0x0 0x0 INDATA Indata 0x38 32 read-write n 0x0 0x0 INTENCLR Interrupt Enable Clear 0x5 8 read-write n 0x0 0x0 ENCCMP Encryption Complete 0 1 GFMCMP GF Multiplication Complete 1 1 INTENSET Interrupt Enable Set 0x6 8 read-write n 0x0 0x0 ENCCMP Encryption Complete 0 1 GFMCMP GF Multiplication Complete 1 1 INTFLAG Interrupt Flag Status 0x7 8 read-write n 0x0 0x0 ENCCMP Encryption Complete 0 1 GFMCMP GF Multiplication Complete 1 1 INTVECTV0 Initialisation Vector n 0x78 32 write-only n 0x0 0x0 INTVECTV1 Initialisation Vector n 0xB8 32 write-only n 0x0 0x0 INTVECTV2 Initialisation Vector n 0xFC 32 write-only n 0x0 0x0 INTVECTV3 Initialisation Vector n 0x144 32 write-only n 0x0 0x0 KEYWORD0 Keyword n 0x18 32 write-only n 0x0 0x0 KEYWORD1 Keyword n 0x28 32 write-only n 0x0 0x0 KEYWORD2 Keyword n 0x3C 32 write-only n 0x0 0x0 KEYWORD3 Keyword n 0x54 32 write-only n 0x0 0x0 KEYWORD4 Keyword n 0x70 32 write-only n 0x0 0x0 KEYWORD5 Keyword n 0x90 32 write-only n 0x0 0x0 KEYWORD6 Keyword n 0xB4 32 write-only n 0x0 0x0 KEYWORD7 Keyword n 0xDC 32 write-only n 0x0 0x0 RANDSEED Random Seed 0x84 32 read-write n 0x0 0x0 CCL Configurable Custom Logic CCL 0x0 0x0 0x40 registers n CTRL Control 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only LUTCTRL0 LUT Control x 0x10 32 read-write n 0x0 0x0 EDGESEL Edge Selection 7 1 ENABLE LUT Enable 1 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0x0 SYNCH Synchronizer enabled 0x1 FILTER Filter enabled 0x2 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0x0 FEEDBACK Feedback input source 0x1 LINK Linked LUT input source 0x2 EVENT Event in put source 0x3 IO I/O pin input source 0x4 AC AC input source 0x5 TC TC input source 0x6 ALTTC Alternate TC input source 0x7 TCC TCC input source 0x8 SERCOM SERCOM inout source 0x9 INSEL1 Input Selection 1 12 4 INSEL2 Input Selection 2 16 4 INVEI Input Event Invert 20 1 LUTEI Event Input Enable 21 1 LUTEO Event Output Enable 22 1 TRUTH Truth Value 24 8 LUTCTRL1 LUT Control x 0x1C 32 read-write n 0x0 0x0 EDGESEL Edge Selection 7 1 ENABLE LUT Enable 1 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0x0 SYNCH Synchronizer enabled 0x1 FILTER Filter enabled 0x2 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0x0 FEEDBACK Feedback input source 0x1 LINK Linked LUT input source 0x2 EVENT Event in put source 0x3 IO I/O pin input source 0x4 AC AC input source 0x5 TC TC input source 0x6 ALTTC Alternate TC input source 0x7 TCC TCC input source 0x8 SERCOM SERCOM inout source 0x9 INSEL1 Input Selection 1 12 4 INSEL2 Input Selection 2 16 4 INVEI Input Event Invert 20 1 LUTEI Event Input Enable 21 1 LUTEO Event Output Enable 22 1 TRUTH Truth Value 24 8 LUTCTRL2 LUT Control x 0x2C 32 read-write n 0x0 0x0 EDGESEL Edge Selection 7 1 ENABLE LUT Enable 1 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0x0 SYNCH Synchronizer enabled 0x1 FILTER Filter enabled 0x2 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0x0 FEEDBACK Feedback input source 0x1 LINK Linked LUT input source 0x2 EVENT Event in put source 0x3 IO I/O pin input source 0x4 AC AC input source 0x5 TC TC input source 0x6 ALTTC Alternate TC input source 0x7 TCC TCC input source 0x8 SERCOM SERCOM inout source 0x9 INSEL1 Input Selection 1 12 4 INSEL2 Input Selection 2 16 4 INVEI Input Event Invert 20 1 LUTEI Event Input Enable 21 1 LUTEO Event Output Enable 22 1 TRUTH Truth Value 24 8 LUTCTRL3 LUT Control x 0x40 32 read-write n 0x0 0x0 EDGESEL Edge Selection 7 1 ENABLE LUT Enable 1 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0x0 SYNCH Synchronizer enabled 0x1 FILTER Filter enabled 0x2 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0x0 FEEDBACK Feedback input source 0x1 LINK Linked LUT input source 0x2 EVENT Event in put source 0x3 IO I/O pin input source 0x4 AC AC input source 0x5 TC TC input source 0x6 ALTTC Alternate TC input source 0x7 TCC TCC input source 0x8 SERCOM SERCOM inout source 0x9 INSEL1 Input Selection 1 12 4 INSEL2 Input Selection 2 16 4 INVEI Input Event Invert 20 1 LUTEI Event Input Enable 21 1 LUTEO Event Output Enable 22 1 TRUTH Truth Value 24 8 SEQCTRL0 SEQ Control x 0x8 8 read-write n 0x0 0x0 SEQSEL Sequential Selection 0 4 SEQSELSelect DISABLE Sequential logic is disabled 0x0 DFF D flip flop 0x1 JK JK flip flop 0x2 LATCH D latch 0x3 RS RS latch 0x4 SEQCTRL1 SEQ Control x 0xD 8 read-write n 0x0 0x0 SEQSEL Sequential Selection 0 4 SEQSELSelect DISABLE Sequential logic is disabled 0x0 DFF D flip flop 0x1 JK JK flip flop 0x2 LATCH D latch 0x3 RS RS latch 0x4 DAC Digital-to-Analog Converter DAC 0x0 0x0 0x20 registers n DAC 24 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable DAC Controller 1 1 SWRST Software Reset 0 1 CTRLB Control B 0x1 8 read-write n 0x0 0x0 DIFF Differential mode enable 0 1 REFSEL Reference Selection for DAC0/1 1 2 REFSELSelect VREFPU External reference unbuffered 0x0 VDDANA Analog supply 0x1 VREFPB External reference buffered 0x2 INTREF Internal bandgap reference 0x3 DACCTRL0 DAC n Control 0x18 16 read-write n 0x0 0x0 CCTRL Current Control 2 2 CCTRLSelect CC12M 1MHz 0x0 CC1M 100kHz 0x1 CC100K 10kHz 0x2 CC10K GCLK_DAC<100kHz 0x3 DITHER Dithering Mode 7 1 ENABLE Enable DAC0 1 1 LEFTADJ Left Adjusted Data 0 1 REFRESH Refresh period 8 4 RUNSTDBY Run in Standby 6 1 DACCTRL1 DAC n Control 0x26 16 read-write n 0x0 0x0 CCTRL Current Control 2 2 CCTRLSelect CC12M 1MHz 0x0 CC1M 100kHz 0x1 CC100K 10kHz 0x2 CC10K GCLK_DAC<100kHz 0x3 DITHER Dithering Mode 7 1 ENABLE Enable DAC0 1 1 LEFTADJ Left Adjusted Data 0 1 REFRESH Refresh period 8 4 RUNSTDBY Run in Standby 6 1 DATA0 DAC n Data 0x20 16 write-only n 0x0 0x0 DATA DAC0 Data 0 16 write-only DATA1 DAC n Data 0x32 16 write-only n 0x0 0x0 DATA DAC0 Data 0 16 write-only DATABUF0 DAC n Data Buffer 0x28 16 write-only n 0x0 0x0 DATABUF DAC0 Data Buffer 0 16 write-only DATABUF1 DAC n Data Buffer 0x3E 16 write-only n 0x0 0x0 DATABUF DAC0 Data Buffer 0 16 write-only DBGCTRL Debug Control 0x18 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 EVCTRL Event Control 0x2 8 read-write n 0x0 0x0 EMPTYEO0 Data Buffer Empty Event Output DAC 0 2 1 EMPTYEO1 Data Buffer Empty Event Output DAC 1 3 1 INVEI0 Enable Invertion of DAC 0 input event 4 1 INVEI1 Enable Invertion of DAC 1 input event 5 1 STARTEI0 Start Conversion Event Input DAC 0 0 1 STARTEI1 Start Conversion Event Input DAC 1 1 1 INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 EMPTY0 Data Buffer 0 Empty Interrupt Enable 2 1 EMPTY1 Data Buffer 1 Empty Interrupt Enable 3 1 UNDERRUN0 Underrun Interrupt Enable for DAC 0 0 1 UNDERRUN1 Underrun Interrupt Enable for DAC 1 1 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 EMPTY0 Data Buffer 0 Empty Interrupt Enable 2 1 EMPTY1 Data Buffer 1 Empty Interrupt Enable 3 1 UNDERRUN0 Underrun Interrupt Enable for DAC 0 0 1 UNDERRUN1 Underrun Interrupt Enable for DAC 1 1 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 EMPTY0 Data Buffer 0 Empty 2 1 EMPTY1 Data Buffer 1 Empty 3 1 UNDERRUN0 DAC 0 Underrun 0 1 UNDERRUN1 DAC 1 Underrun 1 1 STATUS Status 0x7 8 read-only n 0x0 0x0 EOC0 DAC 0 End of Conversion 2 1 read-only EOC1 DAC 1 End of Conversion 3 1 read-only READY0 DAC 0 Startup Ready 0 1 read-only READY1 DAC 1 Startup Ready 1 1 read-only SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 DATA0 Data DAC 0 2 1 read-only DATA1 Data DAC 1 3 1 read-only DATABUF0 Data Buffer DAC 0 4 1 read-only DATABUF1 Data Buffer DAC 1 5 1 read-only ENABLE DAC Enable Status 1 1 read-only SWRST Software Reset 0 1 read-only DMAC Direct Memory Access Controller DMAC 0x0 0x0 0x2C registers n DMAC 5 ACTIVE Active Channel and Levels 0x30 32 read-only n 0x0 0x0 ABUSY Active Channel Busy 15 1 read-only BTCNT Active Channel Block Transfer Count 16 16 read-only ID Active Channel ID 8 5 read-only LVLEX0 Level 0 Channel Trigger Request Executing 0 1 read-only LVLEX1 Level 1 Channel Trigger Request Executing 1 1 read-only LVLEX2 Level 2 Channel Trigger Request Executing 2 1 read-only LVLEX3 Level 3 Channel Trigger Request Executing 3 1 read-only BASEADDR Descriptor Memory Section Base Address 0x34 32 read-write n 0x0 0x0 BASEADDR Descriptor Memory Base Address 0 32 BUSYCH Busy Channels 0x28 32 read-only n 0x0 0x0 BUSYCH0 Busy Channel 0 0 1 read-only BUSYCH1 Busy Channel 1 1 1 read-only BUSYCH10 Busy Channel 10 10 1 read-only BUSYCH11 Busy Channel 11 11 1 read-only BUSYCH12 Busy Channel 12 12 1 read-only BUSYCH13 Busy Channel 13 13 1 read-only BUSYCH14 Busy Channel 14 14 1 read-only BUSYCH15 Busy Channel 15 15 1 read-only BUSYCH2 Busy Channel 2 2 1 read-only BUSYCH3 Busy Channel 3 3 1 read-only BUSYCH4 Busy Channel 4 4 1 read-only BUSYCH5 Busy Channel 5 5 1 read-only BUSYCH6 Busy Channel 6 6 1 read-only BUSYCH7 Busy Channel 7 7 1 read-only BUSYCH8 Busy Channel 8 8 1 read-only BUSYCH9 Busy Channel 9 9 1 read-only CHCTRLA Channel Control A 0x40 8 read-write n 0x0 0x0 ENABLE Channel Enable 1 1 RUNSTDBY Channel run in standby 6 1 SWRST Channel Software Reset 0 1 CHCTRLB Channel Control B 0x44 32 read-write n 0x0 0x0 CMD Software Command 24 2 CMDSelect NOACT No action 0x0 SUSPEND Channel suspend operation 0x1 RESUME Channel resume operation 0x2 EVACT Event Input Action 0 3 EVACTSelect NOACT No action 0x0 TRIG Transfer and periodic transfer trigger 0x1 CTRIG Conditional transfer trigger 0x2 CBLOCK Conditional block transfer 0x3 SUSPEND Channel suspend operation 0x4 RESUME Channel resume operation 0x5 SSKIP Skip next block suspend action 0x6 EVIE Channel Event Input Enable 3 1 EVOE Channel Event Output Enable 4 1 LVL Channel Arbitration Level 5 2 TRIGACT Trigger Action 22 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0x0 BEAT One trigger required for each beat transfer 0x2 TRANSACTION One trigger required for each transaction 0x3 TRIGSRC Trigger Source 8 6 TRIGSRCSelect DISABLE Only software/event triggers 0x0 CHID Channel ID 0x3F 8 read-write n 0x0 0x0 ID Channel ID 0 4 CHINTENCLR Channel Interrupt Enable Clear 0x4C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHINTENSET Channel Interrupt Enable Set 0x4D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHINTFLAG Channel Interrupt Flag Status and Clear 0x4E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHSTATUS Channel Status 0x4F 8 read-only n 0x0 0x0 BUSY Channel Busy 1 1 read-only FERR Channel Fetch Error 2 1 read-only PEND Channel Pending 0 1 read-only CRCCHKSUM CRC Checksum 0x8 32 read-write n 0x0 0x0 CRCCHKSUM CRC Checksum 0 32 CRCCTRL CRC Control 0x2 16 read-write n 0x0 0x0 CRCBEATSIZE CRC Beat Size 0 2 CRCBEATSIZESelect BYTE 8-bit bus transfer 0x0 HWORD 16-bit bus transfer 0x1 WORD 32-bit bus transfer 0x2 CRCPOLY CRC Polynomial Type 2 2 CRCPOLYSelect CRC16 CRC-16 (CRC-CCITT) 0x0 CRC32 CRC32 (IEEE 802.3) 0x1 CRCSRC CRC Input Source 8 6 CRCSRCSelect NOACT No action 0x0 IO I/O interface 0x1 CRCDATAIN CRC Data Input 0x4 32 read-write n 0x0 0x0 CRCDATAIN CRC Data Input 0 32 CRCSTATUS CRC Status 0xC 8 read-write n 0x0 0x0 CRCBUSY CRC Module Busy 0 1 CRCZERO CRC Zero 1 1 read-only CTRL Control 0x0 16 read-write n 0x0 0x0 CRCENABLE CRC Enable 2 1 DMAENABLE DMA Enable 1 1 LVLEN0 Priority Level 0 Enable 8 1 LVLEN1 Priority Level 1 Enable 9 1 LVLEN2 Priority Level 2 Enable 10 1 LVLEN3 Priority Level 3 Enable 11 1 SWRST Software Reset 0 1 DBGCTRL Debug Control 0xD 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 INTPEND Interrupt Pending 0x20 16 read-write n 0x0 0x0 BUSY Busy 14 1 read-only FERR Fetch Error 13 1 read-only ID Channel ID 0 4 PEND Pending 15 1 read-only SUSP Channel Suspend 10 1 TCMPL Transfer Complete 9 1 TERR Transfer Error 8 1 INTSTATUS Interrupt Status 0x24 32 read-only n 0x0 0x0 CHINT0 Channel 0 Pending Interrupt 0 1 read-only CHINT1 Channel 1 Pending Interrupt 1 1 read-only CHINT10 Channel 10 Pending Interrupt 10 1 read-only CHINT11 Channel 11 Pending Interrupt 11 1 read-only CHINT12 Channel 12 Pending Interrupt 12 1 read-only CHINT13 Channel 13 Pending Interrupt 13 1 read-only CHINT14 Channel 14 Pending Interrupt 14 1 read-only CHINT15 Channel 15 Pending Interrupt 15 1 read-only CHINT2 Channel 2 Pending Interrupt 2 1 read-only CHINT3 Channel 3 Pending Interrupt 3 1 read-only CHINT4 Channel 4 Pending Interrupt 4 1 read-only CHINT5 Channel 5 Pending Interrupt 5 1 read-only CHINT6 Channel 6 Pending Interrupt 6 1 read-only CHINT7 Channel 7 Pending Interrupt 7 1 read-only CHINT8 Channel 8 Pending Interrupt 8 1 read-only CHINT9 Channel 9 Pending Interrupt 9 1 read-only PENDCH Pending Channels 0x2C 32 read-only n 0x0 0x0 PENDCH0 Pending Channel 0 0 1 read-only PENDCH1 Pending Channel 1 1 1 read-only PENDCH10 Pending Channel 10 10 1 read-only PENDCH11 Pending Channel 11 11 1 read-only PENDCH12 Pending Channel 12 12 1 read-only PENDCH13 Pending Channel 13 13 1 read-only PENDCH14 Pending Channel 14 14 1 read-only PENDCH15 Pending Channel 15 15 1 read-only PENDCH2 Pending Channel 2 2 1 read-only PENDCH3 Pending Channel 3 3 1 read-only PENDCH4 Pending Channel 4 4 1 read-only PENDCH5 Pending Channel 5 5 1 read-only PENDCH6 Pending Channel 6 6 1 read-only PENDCH7 Pending Channel 7 7 1 read-only PENDCH8 Pending Channel 8 8 1 read-only PENDCH9 Pending Channel 9 9 1 read-only PRICTRL0 Priority Control 0 0x14 32 read-write n 0x0 0x0 LVLPRI0 Level 0 Channel Priority Number 0 4 LVLPRI1 Level 1 Channel Priority Number 8 4 LVLPRI2 Level 2 Channel Priority Number 16 4 LVLPRI3 Level 3 Channel Priority Number 24 4 RRLVLEN0 Level 0 Round-Robin Scheduling Enable 7 1 RRLVLEN1 Level 1 Round-Robin Scheduling Enable 15 1 RRLVLEN2 Level 2 Round-Robin Scheduling Enable 23 1 RRLVLEN3 Level 3 Round-Robin Scheduling Enable 31 1 SWTRIGCTRL Software Trigger Control 0x10 32 read-write n 0x0 0x0 SWTRIG0 Channel 0 Software Trigger 0 1 SWTRIG1 Channel 1 Software Trigger 1 1 SWTRIG10 Channel 10 Software Trigger 10 1 SWTRIG11 Channel 11 Software Trigger 11 1 SWTRIG12 Channel 12 Software Trigger 12 1 SWTRIG13 Channel 13 Software Trigger 13 1 SWTRIG14 Channel 14 Software Trigger 14 1 SWTRIG15 Channel 15 Software Trigger 15 1 SWTRIG2 Channel 2 Software Trigger 2 1 SWTRIG3 Channel 3 Software Trigger 3 1 SWTRIG4 Channel 4 Software Trigger 4 1 SWTRIG5 Channel 5 Software Trigger 5 1 SWTRIG6 Channel 6 Software Trigger 6 1 SWTRIG7 Channel 7 Software Trigger 7 1 SWTRIG8 Channel 8 Software Trigger 8 1 SWTRIG9 Channel 9 Software Trigger 9 1 WRBADDR Write-Back Memory Section Base Address 0x38 32 read-write n 0x0 0x0 WRBADDR Write-Back Memory Base Address 0 32 DSU Device Service Unit DSU 0x0 0x0 0x2000 registers n ADDR Address 0x4 32 read-write n 0x0 0x0 ADDR Address 2 30 AMOD Access Mode 0 2 CID0 Component Identification 0 0x1FF0 32 read-only n 0x0 0x0 PREAMBLEB0 Preamble Byte 0 0 8 read-only CID1 Component Identification 1 0x1FF4 32 read-only n 0x0 0x0 CCLASS Component Class 4 4 read-only PREAMBLE Preamble 0 4 read-only CID2 Component Identification 2 0x1FF8 32 read-only n 0x0 0x0 PREAMBLEB2 Preamble Byte 2 0 8 read-only CID3 Component Identification 3 0x1FFC 32 read-only n 0x0 0x0 PREAMBLEB3 Preamble Byte 3 0 8 CTRL Control 0x0 8 write-only n 0x0 0x0 ARR Auxiliary Row Read 6 1 write-only CE Chip-Erase 4 1 write-only CRC 32-bit Cyclic Redundancy Code 2 1 write-only MBIST Memory built-in self-test 3 1 write-only SMSA Start Memory Stream Access 7 1 write-only SWRST Software Reset 0 1 write-only DATA Data 0xC 32 read-write n 0x0 0x0 DATA Data 0 32 DCC0 Debug Communication Channel n 0x20 32 read-write n 0x0 0x0 DATA Data 0 32 DCC1 Debug Communication Channel n 0x34 32 read-write n 0x0 0x0 DATA Data 0 32 DCFG0 Device Configuration 0x1E0 32 read-write n 0x0 0x0 DCFG Device Configuration 0 32 DCFG1 Device Configuration 0x2D4 32 read-write n 0x0 0x0 DCFG Device Configuration 0 32 DID Device Identification 0x18 32 read-only n 0x0 0x0 DEVSEL Device Select 0 8 read-only DIE Die Number 12 4 read-only FAMILY Family 23 5 read-only FAMILYSelect 0 General purpose microcontroller 0x0 1 PicoPower 0x1 PROCESSOR Processor 28 4 read-only PROCESSORSelect 0 Cortex-M0 0x0 1 Cortex-M0+ 0x1 2 Cortex-M3 0x2 3 Cortex-M4 0x3 REVISION Revision Number 8 4 read-only SERIES Series 16 6 read-only SERIESSelect 0 Cortex-M0+ processor, basic feature set 0x0 1 Cortex-M0+ processor, USB 0x1 END Coresight ROM Table End 0x1008 32 read-only n 0x0 0x0 END End Marker 0 32 ENTRY0 Coresight ROM Table Entry n 0x2000 32 read-only n 0x0 0x0 ADDOFF Address Offset 12 20 read-only EPRES Entry Present 0 1 FMT Format 1 1 read-only ENTRY1 Coresight ROM Table Entry n 0x3004 32 read-only n 0x0 0x0 ADDOFF Address Offset 12 20 read-only EPRES Entry Present 0 1 FMT Format 1 1 read-only LENGTH Length 0x8 32 read-write n 0x0 0x0 LENGTH Length 2 30 MEMTYPE Coresight ROM Table Memory Type 0x1FCC 32 read-only n 0x0 0x0 SMEMP System Memory Present 0 1 PID0 Peripheral Identification 0 0x1FE0 32 read-only n 0x0 0x0 PARTNBL Part Number Low 0 8 PID1 Peripheral Identification 1 0x1FE4 32 read-only n 0x0 0x0 JEPIDCL Low part of the JEP-106 Identity Code 4 4 read-only PARTNBH Part Number High 0 4 PID2 Peripheral Identification 2 0x1FE8 32 read-only n 0x0 0x0 JEPIDCH JEP-106 Identity Code High 0 3 JEPU JEP-106 Identity Code is used 3 1 read-only REVISION Revision Number 4 4 read-only PID3 Peripheral Identification 3 0x1FEC 32 read-only n 0x0 0x0 CUSMOD ARM CUSMOD 0 4 REVAND Revision Number 4 4 read-only PID4 Peripheral Identification 4 0x1FD0 32 read-only n 0x0 0x0 FKBC 4KB count 4 4 read-only JEPCC JEP-106 Continuation Code 0 4 PID5 Peripheral Identification 5 0x1FD4 32 read-only n 0x0 0x0 PID6 Peripheral Identification 6 0x1FD8 32 read-only n 0x0 0x0 PID7 Peripheral Identification 7 0x1FDC 32 read-only n 0x0 0x0 STATUSA Status A 0x1 8 read-write n 0x0 0x0 BERR Bus Error 2 1 CRSTEXT CPU Reset Phase Extension 1 1 DONE Done 0 1 FAIL Failure 3 1 PERR Protection Error 4 1 STATUSB Status B 0x2 8 read-only n 0x0 0x0 DBGPRES Debugger Present 1 1 DCCD0 Debug Communication Channel 0 Dirty 2 1 DCCD1 Debug Communication Channel 1 Dirty 3 1 HPE Hot-Plugging Enable 4 1 PROT Protected 0 1 EIC External Interrupt Controller EIC 0x0 0x0 0x40 registers n EIC 3 ASYNCH EIC Asynchronous edge Detection Enable 0x18 32 read-write n 0x0 0x0 ASYNCH EIC Asynchronous edge Detection Enable 0 16 CONFIG0 Configuration n 0x38 32 read-write n 0x0 0x0 FILTEN0 Filter Enable 0 3 1 FILTEN1 Filter Enable 1 7 1 FILTEN2 Filter Enable 2 11 1 FILTEN3 Filter Enable 3 15 1 FILTEN4 Filter Enable 4 19 1 FILTEN5 Filter Enable 5 23 1 FILTEN6 Filter Enable 6 27 1 FILTEN7 Filter Enable 7 31 1 SENSE0 Input Sense Configuration 0 0 3 SENSE0Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE1 Input Sense Configuration 1 4 3 SENSE1Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE2 Input Sense Configuration 2 8 3 SENSE2Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE3 Input Sense Configuration 3 12 3 SENSE3Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE4 Input Sense Configuration 4 16 3 SENSE4Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE5 Input Sense Configuration 5 20 3 SENSE5Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE6 Input Sense Configuration 6 24 3 SENSE6Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE7 Input Sense Configuration 7 28 3 SENSE7Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 CONFIG1 Configuration n 0x58 32 read-write n 0x0 0x0 FILTEN0 Filter Enable 0 3 1 FILTEN1 Filter Enable 1 7 1 FILTEN2 Filter Enable 2 11 1 FILTEN3 Filter Enable 3 15 1 FILTEN4 Filter Enable 4 19 1 FILTEN5 Filter Enable 5 23 1 FILTEN6 Filter Enable 6 27 1 FILTEN7 Filter Enable 7 31 1 SENSE0 Input Sense Configuration 0 0 3 SENSE0Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE1 Input Sense Configuration 1 4 3 SENSE1Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE2 Input Sense Configuration 2 8 3 SENSE2Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE3 Input Sense Configuration 3 12 3 SENSE3Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE4 Input Sense Configuration 4 16 3 SENSE4Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE5 Input Sense Configuration 5 20 3 SENSE5Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE6 Input Sense Configuration 6 24 3 SENSE6Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE7 Input Sense Configuration 7 28 3 SENSE7Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 CTRLA Control 0x0 8 read-write n 0x0 0x0 CKSEL Clock Selection 4 1 ENABLE Enable 1 1 SWRST Software Reset 0 1 write-only EVCTRL Event Control 0x8 32 read-write n 0x0 0x0 EXTINTEO External Interrupt Event Output Enable 0 16 INTENCLR Interrupt Enable Clear 0xC 32 read-write n 0x0 0x0 EXTINT External Interrupt Disable 0 16 INTENSET Interrupt Enable Set 0x10 32 read-write n 0x0 0x0 EXTINT External Interrupt Disable 0 16 INTFLAG Interrupt Flag Status and Clear 0x14 32 read-write n 0x0 0x0 EXTINT External Interrupt Flag 0 16 NMICTRL NMI Control 0x1 8 read-write n 0x0 0x0 NMIASYNCH NMI Asynchronous edge Detection Enable 4 1 NMIFILTEN NMI Filter Enable 3 1 NMISENSE NMI Input Sense Configuration 0 3 NMISENSESelect NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 NMIFLAG NMI Interrupt Flag 0x2 16 read-write n 0x0 0x0 NMI NMI Interrupt Flag 0 1 SYNCBUSY Syncbusy register 0x4 32 read-only n 0x0 0x0 ENABLE Enable synchronisation 1 1 read-only SWRST Software reset synchronisation 0 1 read-only EVSYS Event System Interface EVSYS 0x0 0x0 0x400 registers n EVSYS 7 CHANNEL0 Channel n 0x40 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL1 Channel n 0x64 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL10 Channel n 0x25C 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL11 Channel n 0x2A8 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL2 Channel n 0x8C 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL3 Channel n 0xB8 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL4 Channel n 0xE8 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL5 Channel n 0x11C 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL6 Channel n 0x154 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL7 Channel n 0x190 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL8 Channel n 0x1D0 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL9 Channel n 0x214 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHSTATUS Channel Status 0xC 32 read-only n 0x0 0x0 CHBUSY0 Channel 0 Busy 16 1 read-only CHBUSY1 Channel 1 Busy 17 1 read-only CHBUSY10 Channel 10 Busy 26 1 read-only CHBUSY11 Channel 11 Busy 27 1 read-only CHBUSY2 Channel 2 Busy 18 1 read-only CHBUSY3 Channel 3 Busy 19 1 read-only CHBUSY4 Channel 4 Busy 20 1 read-only CHBUSY5 Channel 5 Busy 21 1 read-only CHBUSY6 Channel 6 Busy 22 1 read-only CHBUSY7 Channel 7 Busy 23 1 read-only CHBUSY8 Channel 8 Busy 24 1 read-only CHBUSY9 Channel 9 Busy 25 1 read-only USRRDY0 Channel 0 User Ready 0 1 read-only USRRDY1 Channel 1 User Ready 1 1 read-only USRRDY10 Channel 10 User Ready 10 1 read-only USRRDY11 Channel 11 User Ready 11 1 read-only USRRDY2 Channel 2 User Ready 2 1 read-only USRRDY3 Channel 3 User Ready 3 1 read-only USRRDY4 Channel 4 User Ready 4 1 read-only USRRDY5 Channel 5 User Ready 5 1 read-only USRRDY6 Channel 6 User Ready 6 1 read-only USRRDY7 Channel 7 User Ready 7 1 read-only USRRDY8 Channel 8 User Ready 8 1 read-only USRRDY9 Channel 9 User Ready 9 1 read-only CTRLA Control 0x0 8 read-write n 0x0 0x0 SWRST Software Reset 0 1 write-only INTENCLR Interrupt Enable Clear 0x10 32 read-write n 0x0 0x0 EVD0 Channel 0 Event Detection Interrupt Enable 16 1 EVD1 Channel 1 Event Detection Interrupt Enable 17 1 EVD10 Channel 10 Event Detection Interrupt Enable 26 1 EVD11 Channel 11 Event Detection Interrupt Enable 27 1 EVD2 Channel 2 Event Detection Interrupt Enable 18 1 EVD3 Channel 3 Event Detection Interrupt Enable 19 1 EVD4 Channel 4 Event Detection Interrupt Enable 20 1 EVD5 Channel 5 Event Detection Interrupt Enable 21 1 EVD6 Channel 6 Event Detection Interrupt Enable 22 1 EVD7 Channel 7 Event Detection Interrupt Enable 23 1 EVD8 Channel 8 Event Detection Interrupt Enable 24 1 EVD9 Channel 9 Event Detection Interrupt Enable 25 1 OVR0 Channel 0 Overrun Interrupt Enable 0 1 OVR1 Channel 1 Overrun Interrupt Enable 1 1 OVR10 Channel 10 Overrun Interrupt Enable 10 1 OVR11 Channel 11 Overrun Interrupt Enable 11 1 OVR2 Channel 2 Overrun Interrupt Enable 2 1 OVR3 Channel 3 Overrun Interrupt Enable 3 1 OVR4 Channel 4 Overrun Interrupt Enable 4 1 OVR5 Channel 5 Overrun Interrupt Enable 5 1 OVR6 Channel 6 Overrun Interrupt Enable 6 1 OVR7 Channel 7 Overrun Interrupt Enable 7 1 OVR8 Channel 8 Overrun Interrupt Enable 8 1 OVR9 Channel 9 Overrun Interrupt Enable 9 1 INTENSET Interrupt Enable Set 0x14 32 read-write n 0x0 0x0 EVD0 Channel 0 Event Detection Interrupt Enable 16 1 EVD1 Channel 1 Event Detection Interrupt Enable 17 1 EVD10 Channel 10 Event Detection Interrupt Enable 26 1 EVD11 Channel 11 Event Detection Interrupt Enable 27 1 EVD2 Channel 2 Event Detection Interrupt Enable 18 1 EVD3 Channel 3 Event Detection Interrupt Enable 19 1 EVD4 Channel 4 Event Detection Interrupt Enable 20 1 EVD5 Channel 5 Event Detection Interrupt Enable 21 1 EVD6 Channel 6 Event Detection Interrupt Enable 22 1 EVD7 Channel 7 Event Detection Interrupt Enable 23 1 EVD8 Channel 8 Event Detection Interrupt Enable 24 1 EVD9 Channel 9 Event Detection Interrupt Enable 25 1 OVR0 Channel 0 Overrun Interrupt Enable 0 1 OVR1 Channel 1 Overrun Interrupt Enable 1 1 OVR10 Channel 10 Overrun Interrupt Enable 10 1 OVR11 Channel 11 Overrun Interrupt Enable 11 1 OVR2 Channel 2 Overrun Interrupt Enable 2 1 OVR3 Channel 3 Overrun Interrupt Enable 3 1 OVR4 Channel 4 Overrun Interrupt Enable 4 1 OVR5 Channel 5 Overrun Interrupt Enable 5 1 OVR6 Channel 6 Overrun Interrupt Enable 6 1 OVR7 Channel 7 Overrun Interrupt Enable 7 1 OVR8 Channel 8 Overrun Interrupt Enable 8 1 OVR9 Channel 9 Overrun Interrupt Enable 9 1 INTFLAG Interrupt Flag Status and Clear 0x18 32 read-write n 0x0 0x0 EVD0 Channel 0 Event Detection 16 1 EVD1 Channel 1 Event Detection 17 1 EVD10 Channel 10 Event Detection 26 1 EVD11 Channel 11 Event Detection 27 1 EVD2 Channel 2 Event Detection 18 1 EVD3 Channel 3 Event Detection 19 1 EVD4 Channel 4 Event Detection 20 1 EVD5 Channel 5 Event Detection 21 1 EVD6 Channel 6 Event Detection 22 1 EVD7 Channel 7 Event Detection 23 1 EVD8 Channel 8 Event Detection 24 1 EVD9 Channel 9 Event Detection 25 1 OVR0 Channel 0 Overrun 0 1 OVR1 Channel 1 Overrun 1 1 OVR10 Channel 10 Overrun 10 1 OVR11 Channel 11 Overrun 11 1 OVR2 Channel 2 Overrun 2 1 OVR3 Channel 3 Overrun 3 1 OVR4 Channel 4 Overrun 4 1 OVR5 Channel 5 Overrun 5 1 OVR6 Channel 6 Overrun 6 1 OVR7 Channel 7 Overrun 7 1 OVR8 Channel 8 Overrun 8 1 OVR9 Channel 9 Overrun 9 1 SWEVT Software Event 0x1C 32 write-only n 0x0 0x0 CHANNEL0 Channel 0 Software Selection 0 1 CHANNEL1 Channel 1 Software Selection 1 1 CHANNEL10 Channel 10 Software Selection 10 1 CHANNEL11 Channel 11 Software Selection 11 1 CHANNEL2 Channel 2 Software Selection 2 1 CHANNEL3 Channel 3 Software Selection 3 1 CHANNEL4 Channel 4 Software Selection 4 1 CHANNEL5 Channel 5 Software Selection 5 1 CHANNEL6 Channel 6 Software Selection 6 1 CHANNEL7 Channel 7 Software Selection 7 1 CHANNEL8 Channel 8 Software Selection 8 1 CHANNEL9 Channel 9 Software Selection 9 1 USER0 User Multiplexer n 0x100 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER1 User Multiplexer n 0x184 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER10 User Multiplexer n 0x6DC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER11 User Multiplexer n 0x788 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER12 User Multiplexer n 0x838 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER13 User Multiplexer n 0x8EC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER14 User Multiplexer n 0x9A4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER15 User Multiplexer n 0xA60 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER16 User Multiplexer n 0xB20 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER17 User Multiplexer n 0xBE4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER18 User Multiplexer n 0xCAC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER19 User Multiplexer n 0xD78 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER2 User Multiplexer n 0x20C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER20 User Multiplexer n 0xE48 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER21 User Multiplexer n 0xF1C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER22 User Multiplexer n 0xFF4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER23 User Multiplexer n 0x10D0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER24 User Multiplexer n 0x11B0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER25 User Multiplexer n 0x1294 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER26 User Multiplexer n 0x137C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER27 User Multiplexer n 0x1468 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER28 User Multiplexer n 0x1558 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER29 User Multiplexer n 0x164C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER3 User Multiplexer n 0x298 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER30 User Multiplexer n 0x1744 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER31 User Multiplexer n 0x1840 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER32 User Multiplexer n 0x1940 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER33 User Multiplexer n 0x1A44 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER34 User Multiplexer n 0x1B4C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER35 User Multiplexer n 0x1C58 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER36 User Multiplexer n 0x1D68 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER37 User Multiplexer n 0x1E7C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER38 User Multiplexer n 0x1F94 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER39 User Multiplexer n 0x20B0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER4 User Multiplexer n 0x328 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER40 User Multiplexer n 0x21D0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER41 User Multiplexer n 0x22F4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER42 User Multiplexer n 0x241C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER43 User Multiplexer n 0x2548 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER44 User Multiplexer n 0x2678 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER5 User Multiplexer n 0x3BC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER6 User Multiplexer n 0x454 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER7 User Multiplexer n 0x4F0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER8 User Multiplexer n 0x590 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER9 User Multiplexer n 0x634 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 GCLK Generic Clock Generator GCLK 0x0 0x0 0x200 registers n CTRLA Control 0x0 8 read-write n 0x0 0x0 SWRST Software Reset 0 1 GENCTRL0 Generic Clock Generator Control 0x40 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC16M OSC16M oscillator output 0x6 DFLL48M DFLL48M output 0x7 DPLL96M DPLL96M output 0x8 GENCTRL1 Generic Clock Generator Control 0x64 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC16M OSC16M oscillator output 0x6 DFLL48M DFLL48M output 0x7 DPLL96M DPLL96M output 0x8 GENCTRL2 Generic Clock Generator Control 0x8C 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC16M OSC16M oscillator output 0x6 DFLL48M DFLL48M output 0x7 DPLL96M DPLL96M output 0x8 GENCTRL3 Generic Clock Generator Control 0xB8 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC16M OSC16M oscillator output 0x6 DFLL48M DFLL48M output 0x7 DPLL96M DPLL96M output 0x8 GENCTRL4 Generic Clock Generator Control 0xE8 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC16M OSC16M oscillator output 0x6 DFLL48M DFLL48M output 0x7 DPLL96M DPLL96M output 0x8 GENCTRL5 Generic Clock Generator Control 0x11C 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC16M OSC16M oscillator output 0x6 DFLL48M DFLL48M output 0x7 DPLL96M DPLL96M output 0x8 GENCTRL6 Generic Clock Generator Control 0x154 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC16M OSC16M oscillator output 0x6 DFLL48M DFLL48M output 0x7 DPLL96M DPLL96M output 0x8 GENCTRL7 Generic Clock Generator Control 0x190 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC16M OSC16M oscillator output 0x6 DFLL48M DFLL48M output 0x7 DPLL96M DPLL96M output 0x8 GENCTRL8 Generic Clock Generator Control 0x1D0 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC16M OSC16M oscillator output 0x6 DFLL48M DFLL48M output 0x7 DPLL96M DPLL96M output 0x8 PCHCTRL0 Peripheral Clock Control 0x100 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL1 Peripheral Clock Control 0x184 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL10 Peripheral Clock Control 0x6DC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL11 Peripheral Clock Control 0x788 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL12 Peripheral Clock Control 0x838 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL13 Peripheral Clock Control 0x8EC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL14 Peripheral Clock Control 0x9A4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL15 Peripheral Clock Control 0xA60 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL16 Peripheral Clock Control 0xB20 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL17 Peripheral Clock Control 0xBE4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL18 Peripheral Clock Control 0xCAC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL19 Peripheral Clock Control 0xD78 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL2 Peripheral Clock Control 0x20C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL20 Peripheral Clock Control 0xE48 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL21 Peripheral Clock Control 0xF1C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL22 Peripheral Clock Control 0xFF4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL23 Peripheral Clock Control 0x10D0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL24 Peripheral Clock Control 0x11B0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL25 Peripheral Clock Control 0x1294 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL26 Peripheral Clock Control 0x137C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL27 Peripheral Clock Control 0x1468 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL28 Peripheral Clock Control 0x1558 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL29 Peripheral Clock Control 0x164C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL3 Peripheral Clock Control 0x298 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL30 Peripheral Clock Control 0x1744 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL31 Peripheral Clock Control 0x1840 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL32 Peripheral Clock Control 0x1940 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL33 Peripheral Clock Control 0x1A44 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL34 Peripheral Clock Control 0x1B4C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL35 Peripheral Clock Control 0x1C58 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL4 Peripheral Clock Control 0x328 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL5 Peripheral Clock Control 0x3BC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL6 Peripheral Clock Control 0x454 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL7 Peripheral Clock Control 0x4F0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL8 Peripheral Clock Control 0x590 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL9 Peripheral Clock Control 0x634 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 SYNCBUSY Synchronization Busy 0x4 32 read-only n 0x0 0x0 GENCTRL Generic Clock Generator Control Synchronization Busy bits 2 9 read-only GENCTRLSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 SWRST Software Reset Synchroniation Busy bit 0 1 read-only MCLK Main Clock MCLK 0x0 0x0 0x2C registers n SYSTEM 0 AHBMASK AHB Mask 0x10 32 read-write n 0x0 0x0 DMAC_ DMAC AHB Clock Mask 11 1 DSU_ DSU AHB Clock Mask 5 1 H2LBRIDGES_H_ H2LBRIDGES_H AHB Clock Mask 17 1 HMCRAMCHS_ HMCRAMCHS AHB Clock Mask 9 1 HMCRAMCHS_AHBSETUPKEEPER_ HMCRAMCHS_AHBSETUPKEEPER AHB Clock Mask 18 1 HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_ HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE AHB Clock Mask 19 1 HMCRAMCLP_ HMCRAMCLP AHB Clock Mask 10 1 HPB0_ HPB0 AHB Clock Mask 0 1 HPB1_ HPB1 AHB Clock Mask 1 1 HPB2_ HPB2 AHB Clock Mask 2 1 HPB3_ HPB3 AHB Clock Mask 3 1 HPB4_ HPB4 AHB Clock Mask 4 1 L2HBRIDGES_H_ L2HBRIDGES_H AHB Clock Mask 16 1 NVMCTRL_ NVMCTRL AHB Clock Mask 8 1 NVMCTRL_PICACHU_ NVMCTRL_PICACHU AHB Clock Mask 15 1 PAC_ PAC AHB Clock Mask 14 1 PICOPRAM_ PICOPRAM AHB Clock Mask 13 1 USB_ USB AHB Clock Mask 12 1 APBAMASK APBA Mask 0x14 32 read-write n 0x0 0x0 EIC_ EIC APB Clock Enable 9 1 GCLK_ GCLK APB Clock Enable 6 1 MCLK_ MCLK APB Clock Enable 1 1 OSC32KCTRL_ OSC32KCTRL APB Clock Enable 4 1 OSCCTRL_ OSCCTRL APB Clock Enable 3 1 PM_ PM APB Clock Enable 0 1 PORT_ PORT APB Clock Enable 10 1 RSTC_ RSTC APB Clock Enable 2 1 RTC_ RTC APB Clock Enable 8 1 SUPC_ SUPC APB Clock Enable 5 1 TAL_ TAL APB Clock Enable 11 1 WDT_ WDT APB Clock Enable 7 1 APBBMASK APBB Mask 0x18 32 read-write n 0x0 0x0 DSU_ DSU APB Clock Enable 1 1 NVMCTRL_ NVMCTRL APB Clock Enable 2 1 USB_ USB APB Clock Enable 0 1 APBCMASK APBC Mask 0x1C 32 read-write n 0x0 0x0 AES_ AES APB Clock Enable 13 1 DAC_ DAC APB Clock Enable 12 1 SERCOM0_ SERCOM0 APB Clock Enable 0 1 SERCOM1_ SERCOM1 APB Clock Enable 1 1 SERCOM2_ SERCOM2 APB Clock Enable 2 1 SERCOM3_ SERCOM3 APB Clock Enable 3 1 SERCOM4_ SERCOM4 APB Clock Enable 4 1 TC0_ TC0 APB Clock Enable 8 1 TC1_ TC1 APB Clock Enable 9 1 TCC0_ TCC0 APB Clock Enable 5 1 TCC1_ TCC1 APB Clock Enable 6 1 TCC2_ TCC2 APB Clock Enable 7 1 TRNG_ TRNG APB Clock Enable 14 1 APBDMASK APBD Mask 0x20 32 read-write n 0x0 0x0 AC_ AC APB Clock Enable 4 1 ADC_ ADC APB Clock Enable 3 1 CCL_ CCL APB Clock Enable 7 1 EVSYS_ EVSYS APB Clock Enable 0 1 OPAMP_ OPAMP APB Clock Enable 6 1 PTC_ PTC APB Clock Enable 5 1 SERCOM5_ SERCOM5 APB Clock Enable 1 1 TC4_ TC4 APB Clock Enable 2 1 APBEMASK APBE Mask 0x24 32 read-write n 0x0 0x0 PAC_ PAC APB Clock Enable 0 1 BUPDIV Backup Clock Division 0x6 8 read-write n 0x0 0x0 BUPDIV Backup Clock Division Factor 0 8 BUPDIVSelect DIV1 Divide by 1 0x1 DIV16 Divide by 16 0x10 DIV2 Divide by 2 0x2 DIV32 Divide by 32 0x20 DIV4 Divide by 4 0x4 DIV64 Divide by 64 0x40 DIV8 Divide by 8 0x8 DIV128 Divide by 128 0x80 CPUDIV CPU Clock Division 0x4 8 read-write n 0x0 0x0 CPUDIV CPU Clock Division Factor 0 8 CPUDIVSelect DIV1 Divide by 1 0x1 DIV16 Divide by 16 0x10 DIV2 Divide by 2 0x2 DIV32 Divide by 32 0x20 DIV4 Divide by 4 0x4 DIV64 Divide by 64 0x40 DIV8 Divide by 8 0x8 DIV128 Divide by 128 0x80 CTRLA Control A 0x0 8 read-write n 0x0 0x0 CFDEN Clock Failure Detector Enable 2 1 EMCLK Emergency Clock Select 4 1 INTENCLR Interrupt Enable Clear 0x1 8 read-write n 0x0 0x0 CFD Clock Failure Detector Interrupt Enable 1 1 CKRDY Clock Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x2 8 read-write n 0x0 0x0 CFD Clock Failure Detector Interrupt Enable 1 1 CKRDY Clock Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x3 8 read-write n 0x0 0x0 CFD Clock Failure Detector 1 1 CKRDY Clock Ready 0 1 LPDIV Low-Power Clock Division 0x5 8 read-write n 0x0 0x0 LPDIV Low-Power Clock Division Factor 0 8 LPDIVSelect DIV1 Divide by 1 0x1 DIV16 Divide by 16 0x10 DIV2 Divide by 2 0x2 DIV32 Divide by 32 0x20 DIV4 Divide by 4 0x4 DIV64 Divide by 64 0x40 DIV8 Divide by 8 0x8 DIV128 Divide by 128 0x80 MTB Cortex-M0+ Micro-Trace Buffer MTB 0x0 0x0 0x1000 registers n AUTHSTATUS MTB Authentication Status 0xFB8 32 read-only n 0x0 0x0 BASE MTB Base 0xC 32 read-only n 0x0 0x0 CID0 Component Identification 0 0xFF0 32 read-only n 0x0 0x0 CID1 Component Identification 1 0xFF4 32 read-only n 0x0 0x0 CID2 Component Identification 2 0xFF8 32 read-only n 0x0 0x0 CID3 Component Identification 3 0xFFC 32 read-only n 0x0 0x0 CLAIMCLR MTB Claim Clear 0xFA4 32 read-write n 0x0 0x0 CLAIMSET MTB Claim Set 0xFA0 32 read-write n 0x0 0x0 DEVARCH MTB Device Architecture 0xFBC 32 read-only n 0x0 0x0 DEVID MTB Device Configuration 0xFC8 32 read-only n 0x0 0x0 DEVTYPE MTB Device Type 0xFCC 32 read-only n 0x0 0x0 FLOW MTB Flow 0x8 32 read-write n 0x0 0x0 AUTOHALT Auto Halt Request 1 1 AUTOSTOP Auto Stop Tracing 0 1 WATERMARK Watermark value 3 29 ITCTRL MTB Integration Mode Control 0xF00 32 read-write n 0x0 0x0 LOCKACCESS MTB Lock Access 0xFB0 32 read-write n 0x0 0x0 LOCKSTATUS MTB Lock Status 0xFB4 32 read-only n 0x0 0x0 MASTER MTB Master 0x4 32 read-write n 0x0 0x0 EN Main Trace Enable 31 1 HALTREQ Halt Request 9 1 MASK Maximum Value of the Trace Buffer in SRAM 0 5 RAMPRIV SRAM Privilege 8 1 SFRWPRIV Special Function Register Write Privilege 7 1 TSTARTEN Trace Start Input Enable 5 1 TSTOPEN Trace Stop Input Enable 6 1 PID0 Peripheral Identification 0 0xFE0 32 read-only n 0x0 0x0 PID1 Peripheral Identification 1 0xFE4 32 read-only n 0x0 0x0 PID2 Peripheral Identification 2 0xFE8 32 read-only n 0x0 0x0 PID3 Peripheral Identification 3 0xFEC 32 read-only n 0x0 0x0 PID4 Peripheral Identification 4 0xFD0 32 read-only n 0x0 0x0 PID5 Peripheral Identification 5 0xFD4 32 read-only n 0x0 0x0 PID6 Peripheral Identification 6 0xFD8 32 read-only n 0x0 0x0 PID7 Peripheral Identification 7 0xFDC 32 read-only n 0x0 0x0 POSITION MTB Position 0x0 32 read-write n 0x0 0x0 POINTER Trace Packet Location Pointer 3 29 WRAP Pointer Value Wraps 2 1 NVMCTRL Non-Volatile Memory Controller NVMCTRL 0x0 0x0 0x2C registers n NVMCTRL 4 ADDR Address 0x1C 32 read-write n 0x0 0x0 ADDR NVM Address 0 22 CTRLA Control A 0x0 16 read-write n 0x0 0x0 CMD Command 0 7 CMDSelect RWWEEER RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. 0x1a RWWEEWP RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. 0x1c ER Erase Row - Erases the row addressed by the ADDR register. 0x2 WP Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. 0x4 LR Lock Region - Locks the region containing the address location in the ADDR register. 0x40 UR Unlock Region - Unlocks the region containing the address location in the ADDR register. 0x41 SPRM Sets the power reduction mode. 0x42 CPRM Clears the power reduction mode. 0x43 PBC Page Buffer Clear - Clears the page buffer. 0x44 SSB Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. 0x45 INVALL Invalidate all cache lines. 0x46 EAR Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. 0x5 WAP Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. 0x6 SF Security Flow Command 0xa WL Write lockbits 0xf CMDEX Command Execution 8 8 CMDEXSelect KEY Execution Key 0xa5 CTRLB Control B 0x4 32 read-write n 0x0 0x0 CACHEDIS Cache Disable 18 1 FWUP fast wake-up 11 1 MANW Manual Write 7 1 READMODE NVMCTRL Read Mode 16 2 READMODESelect NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. 0x0 LOW_POWER Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. 0x1 DETERMINISTIC The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. 0x2 RWS NVM Read Wait States 1 4 RWSSelect SINGLE Single Auto Wait State 0x0 HALF Half Auto Wait State 0x1 DUAL Dual Auto Wait State 0x2 SLEEPPRM Power Reduction Mode during Sleep 8 2 SLEEPPRMSelect WAKEONACCESS NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. 0x0 WAKEUPINSTANT NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. 0x1 DISABLED Auto power reduction disabled. 0x3 INTENCLR Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERROR Error Interrupt Enable 1 1 READY NVM Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x10 8 read-write n 0x0 0x0 ERROR Error Interrupt Enable 1 1 READY NVM Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x14 8 read-write n 0x0 0x0 ERROR Error 1 1 READY NVM Ready 0 1 LOCK Lock Section 0x20 16 read-write n 0x0 0x0 LOCK Region Lock Bits 0 16 read-only PARAM NVM Parameter 0x8 32 read-write n 0x0 0x0 NVMP NVM Pages 0 16 read-only PSZ Page Size 16 3 read-only PSZSelect 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 RWWEEP RWW EEPROM Pages 20 12 read-only STATUS Status 0x18 16 read-write n 0x0 0x0 LOAD NVM Page Buffer Active Loading 1 1 LOCKE Lock Error Status 3 1 NVME NVM Error 4 1 PRM Power Reduction Mode 0 1 read-only PROGE Programming Error Status 2 1 SB Security Bit Status 8 1 read-only OPAMP Operational Amplifier OPAMP 0x0 0x0 0x10 registers n CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 LPMUX Low-Power Mux 7 1 SWRST Software Reset 0 1 OPAMPCTRL0 OPAMP n Control 0x8 32 read-write n 0x0 0x0 ANAOUT Analog Output 2 1 BIAS Bias Selection 3 2 ENABLE Operational Amplifier Enable 1 1 MUXNEG Negative Input Mux Selection 20 3 MUXPOS Positive Input Mux Selection 16 3 ONDEMAND On Demand Control 7 1 POTMUX Potentiometer Selection 13 3 RES1EN Resistor 1 Enable 10 1 RES1MUX Resistor 1 Mux 11 2 RES2OUT Resistor ladder To Output 8 1 RES2VCC Resistor ladder To VCC 9 1 RUNSTDBY Run in Standby 6 1 OPAMPCTRL1 OPAMP n Control 0x10 32 read-write n 0x0 0x0 ANAOUT Analog Output 2 1 BIAS Bias Selection 3 2 ENABLE Operational Amplifier Enable 1 1 MUXNEG Negative Input Mux Selection 20 3 MUXPOS Positive Input Mux Selection 16 3 ONDEMAND On Demand Control 7 1 POTMUX Potentiometer Selection 13 3 RES1EN Resistor 1 Enable 10 1 RES1MUX Resistor 1 Mux 11 2 RES2OUT Resistor ladder To Output 8 1 RES2VCC Resistor ladder To VCC 9 1 RUNSTDBY Run in Standby 6 1 OPAMPCTRL2 OPAMP n Control 0x1C 32 read-write n 0x0 0x0 ANAOUT Analog Output 2 1 BIAS Bias Selection 3 2 ENABLE Operational Amplifier Enable 1 1 MUXNEG Negative Input Mux Selection 20 3 MUXPOS Positive Input Mux Selection 16 3 ONDEMAND On Demand Control 7 1 POTMUX Potentiometer Selection 13 3 RES1EN Resistor 1 Enable 10 1 RES1MUX Resistor 1 Mux 11 2 RES2OUT Resistor ladder To Output 8 1 RES2VCC Resistor ladder To VCC 9 1 RUNSTDBY Run in Standby 6 1 STATUS Status 0x2 8 read-only n 0x0 0x0 READY0 OPAMP 0 Ready 0 1 READY1 OPAMP 1 Ready 1 1 READY2 OPAMP 2 Ready 2 1 OSC32KCTRL 32k Oscillators Control OSC32KCTRL 0x0 0x0 0x2C registers n SYSTEM 0 INTENCLR Interrupt Enable Clear 0x0 32 read-write n 0x0 0x0 OSC32KRDY OSC32K Ready Interrupt Enable 1 1 XOSC32KRDY XOSC32K Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x4 32 read-write n 0x0 0x0 OSC32KRDY OSC32K Ready Interrupt Enable 1 1 XOSC32KRDY XOSC32K Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x8 32 read-write n 0x0 0x0 OSC32KRDY OSC32K Ready 1 1 XOSC32KRDY XOSC32K Ready 0 1 OSC32K 32kHz Internal Oscillator (OSC32K) Control 0x18 32 read-write n 0x0 0x0 CALIB Oscillator Calibration 16 7 EN1K 1kHz Output Enable 3 1 EN32K 32kHz Output Enable 2 1 ENABLE Oscillator Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 STARTUP Oscillator Start-Up Time 8 3 WRTLOCK Write Lock 12 1 OSCULP32K 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control 0x1C 32 read-write n 0x0 0x0 CALIB Oscillator Calibration 8 5 EN1K Enable Out 1k 2 1 EN32K Enable Out 32k 1 1 WRTLOCK Write Lock 15 1 RTCCTRL Clock selection 0x10 32 read-write n 0x0 0x0 RTCSEL RTC Clock Selection 0 3 RTCSELSelect ULP1K 1.024kHz from 32kHz internal ULP oscillator 0x0 ULP32K 32.768kHz from 32kHz internal ULP oscillator 0x1 OSC1K 1.024kHz from 32.768kHz internal oscillator 0x2 OSC32K 32.768kHz from 32.768kHz internal oscillator 0x3 XOSC1K 1.024kHz from 32.768kHz internal oscillator 0x4 XOSC32K 32.768kHz from 32.768kHz external crystal oscillator 0x5 STATUS Power and Clocks Status 0xC 32 read-only n 0x0 0x0 OSC32KRDY OSC32K Ready 1 1 read-only XOSC32KRDY XOSC32K Ready 0 1 read-only XOSC32K 32kHz External Crystal Oscillator (XOSC32K) Control 0x14 32 read-write n 0x0 0x0 EN1K 1kHz Output Enable 4 1 EN32K 32kHz Output Enable 3 1 ENABLE Oscillator Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 STARTUP Oscillator Start-Up Time 8 3 WRTLOCK Write Lock 12 1 XTALEN Crystal Oscillator Enable 2 1 OSCCTRL Oscillators Control OSCCTRL 0x0 0x0 0x2C registers n SYSTEM 0 DFLLCTRL DFLL48M Control 0x18 16 read-write n 0x0 0x0 BPLCKC Bypass Coarse Lock 10 1 CCDIS Chill Cycle Disable 8 1 ENABLE DFLL Enable 1 1 LLAW Lose Lock After Wake 4 1 MODE Operating Mode Selection 2 1 ONDEMAND On Demand Control 7 1 QLDIS Quick Lock Disable 9 1 RUNSTDBY Run in Standby 6 1 STABLE Stable DFLL Frequency 3 1 USBCRM USB Clock Recovery Mode 5 1 WAITLOCK Wait Lock 11 1 DFLLMUL DFLL48M Multiplier 0x20 32 read-write n 0x0 0x0 CSTEP Coarse Maximum Step 26 6 FSTEP Fine Maximum Step 16 10 MUL DFLL Multiply Factor 0 16 DFLLSYNC DFLL48M Synchronization 0x24 8 read-write n 0x0 0x0 READREQ Read Request 7 1 write-only DFLLVAL DFLL48M Value 0x1C 32 read-write n 0x0 0x0 COARSE Coarse Value 10 6 DIFF Multiplication Ratio Difference 16 16 read-only FINE Fine Value 0 10 DPLLCTRLA DPLL Control 0x28 8 read-write n 0x0 0x0 ENABLE Enable 1 1 ONDEMAND On Demand 7 1 RUNSTDBY Run in Standby 6 1 DPLLCTRLB Digital Core Configuration 0x30 32 read-write n 0x0 0x0 DIV Clock Divider 16 11 FILTER Proportional Integral Filter Selection 0 2 LBYPASS Lock Bypass 12 1 LPEN Low-Power Enable 2 1 LTIME Lock Time 8 3 REFCLK Reference Clock Selection 4 2 WUF Wake Up Fast 3 1 DPLLPRESC DPLL Prescaler 0x34 8 read-write n 0x0 0x0 PRESC Output Clock Prescaler 0 2 PRESCSelect DIV1 DPLL output is divided by 1 0x0 DIV2 DPLL output is divided by 2 0x1 DIV4 DPLL output is divided by 4 0x2 DPLLRATIO DPLL Ratio Control 0x2C 32 read-write n 0x0 0x0 LDR Loop Divider Ratio 0 12 LDRFRAC Loop Divider Ratio Fractional Part 16 4 DPLLSTATUS DPLL Status 0x3C 8 read-only n 0x0 0x0 CLKRDY DPLL Clock Ready 1 1 read-only LOCK DPLL Lock Status 0 1 read-only DPLLSYNCBUSY DPLL Synchronization Busy 0x38 8 read-only n 0x0 0x0 DPLLPRESC DPLL Prescaler Synchronization Status 3 1 read-only DPLLRATIO DPLL Ratio Synchronization Status 2 1 read-only ENABLE DPLL Enable Synchronization Status 1 1 read-only INTENCLR Interrupt Enable Clear 0x0 32 read-write n 0x0 0x0 DFLLLCKC DFLL Lock Coarse Interrupt Enable 11 1 DFLLLCKF DFLL Lock Fine Interrupt Enable 10 1 DFLLOOB DFLL Out Of Bounds Interrupt Enable 9 1 DFLLRCS DFLL Reference Clock Stopped Interrupt Enable 12 1 DFLLRDY DFLL Ready Interrupt Enable 8 1 DPLLLCKF DPLL Lock Fall Interrupt Enable 17 1 DPLLLCKR DPLL Lock Rise Interrupt Enable 16 1 DPLLLDRTO DPLL Ratio Ready Interrupt Enable 19 1 DPLLLTO DPLL Time Out Interrupt Enable 18 1 OSC16MRDY OSC16M Ready Interrupt Enable 4 1 XOSCRDY XOSC Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x4 32 read-write n 0x0 0x0 DFLLLCKC DFLL Lock Coarse Interrupt Enable 11 1 DFLLLCKF DFLL Lock Fine Interrupt Enable 10 1 DFLLOOB DFLL Out Of Bounds Interrupt Enable 9 1 DFLLRCS DFLL Reference Clock Stopped Interrupt Enable 12 1 DFLLRDY DFLL Ready Interrupt Enable 8 1 DPLLLCKF DPLL Lock Fall Interrupt Enable 17 1 DPLLLCKR DPLL Lock Rise Interrupt Enable 16 1 DPLLLDRTO DPLL Ratio Ready Interrupt Enable 19 1 DPLLLTO DPLL Time Out Interrupt Enable 18 1 OSC16MRDY OSC16M Ready Interrupt Enable 4 1 XOSCRDY XOSC Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x8 32 read-write n 0x0 0x0 DFLLLCKC DFLL Lock Coarse 11 1 DFLLLCKF DFLL Lock Fine 10 1 DFLLOOB DFLL Out Of Bounds 9 1 DFLLRCS DFLL Reference Clock Stopped 12 1 DFLLRDY DFLL Ready 8 1 DPLLLCKF DPLL Lock Fall 17 1 DPLLLCKR DPLL Lock Rise 16 1 DPLLLDRTO DPLL Ratio Ready 19 1 DPLLLTO DPLL Timeout 18 1 OSC16MRDY OSC16M Ready 4 1 XOSCRDY XOSC Ready 0 1 OSC16MCTRL 16MHz Internal Oscillator (OSC16M) Control 0x14 8 read-write n 0x0 0x0 ENABLE Oscillator Enable 1 1 FSEL Oscillator Frequency Select 2 2 FSELSelect 4 4MHz 0x0 8 8MHz 0x1 12 12MHz 0x2 16 16MHz 0x3 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 STATUS Power and Clocks Status 0xC 32 read-only n 0x0 0x0 DFLLLCKC DFLL Lock Coarse 11 1 read-only DFLLLCKF DFLL Lock Fine 10 1 read-only DFLLOOB DFLL Out Of Bounds 9 1 read-only DFLLRCS DFLL Reference Clock Stopped 12 1 read-only DFLLRDY DFLL Ready 8 1 read-only DPLLLCKF DPLL Lock Fall 17 1 read-only DPLLLCKR DPLL Lock Rise 16 1 read-only DPLLLDRTO DPLL Ratio Ready 19 1 read-only DPLLTO DPLL Timeout 18 1 read-only OSC16MRDY OSC16M Ready 4 1 read-only XOSCRDY XOSC Ready 0 1 read-only XOSCCTRL External Multipurpose Crystal Oscillator (XOSC) Control 0x10 16 read-write n 0x0 0x0 AMPGC Automatic Amplitude Gain Control 11 1 ENABLE Oscillator Enable 1 1 GAIN Oscillator Gain 8 3 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 STARTUP Start-Up Time 12 4 XTALEN Crystal Oscillator Enable 2 1 PAC Peripheral Access Controller PAC 0x0 0x0 0x2C registers n SYSTEM 0 EVCTRL Event control 0x4 8 read-write n 0x0 0x0 ERREO Peripheral acess error event output 0 1 INTENCLR Interrupt enable clear 0x8 8 read-write n 0x0 0x0 ERR Peripheral access error interrupt disable 0 1 INTENSET Interrupt enable set 0x9 8 read-write n 0x0 0x0 ERR Peripheral access error interrupt enable 0 1 INTFLAGA Peripheral interrupt flag status - Bridge A 0x14 32 read-write n 0x0 0x0 EIC_ EIC 9 1 GCLK_ GCLK 6 1 MCLK_ MCLK 1 1 OSC32KCTRL_ OSC32KCTRL 4 1 OSCCTRL_ OSCCTRL 3 1 PM_ PM 0 1 PORT_ PORT 10 1 RSTC_ RSTC 2 1 RTC_ RTC 8 1 SUPC_ SUPC 5 1 TAL_ TAL 11 1 WDT_ WDT 7 1 INTFLAGAHB Bridge interrupt flag status 0x10 32 read-write n 0x0 0x0 FLASH_ FLASH 0 1 H2LBRIDGES_ H2LBRIDGES 4 1 HPB0_ HPB0 16 1 HPB1_ HPB1 3 1 HPB2_ HPB2 17 1 HPB3_ HPB3 18 1 HPB4_ HPB4 19 1 HSRAMCM0P_ HSRAMCM0P 1 1 HSRAMDSU_ HSRAMDSU 2 1 HSRAMLP_ HSRAMLP 25 1 L2HBRIDGES_ L2HBRIDGES 24 1 LPRAMDMAC_ LPRAMDMAC 23 1 LPRAMHS_ LPRAMHS 21 1 LPRAMPICOP_ LPRAMPICOP 22 1 PICOPRAM_ PICOPRAM 20 1 INTFLAGB Peripheral interrupt flag status - Bridge B 0x18 32 read-write n 0x0 0x0 DSU_ DSU 1 1 MTB_ MTB 3 1 NVMCTRL_ NVMCTRL 2 1 USB_ USB 0 1 INTFLAGC Peripheral interrupt flag status - Bridge C 0x1C 32 read-write n 0x0 0x0 AES_ AES 13 1 DAC_ DAC 12 1 SERCOM0_ SERCOM0 0 1 SERCOM1_ SERCOM1 1 1 SERCOM2_ SERCOM2 2 1 SERCOM3_ SERCOM3 3 1 SERCOM4_ SERCOM4 4 1 TC0_ TC0 8 1 TC1_ TC1 9 1 TCC0_ TCC0 5 1 TCC1_ TCC1 6 1 TCC2_ TCC2 7 1 TRNG_ TRNG 14 1 INTFLAGD Peripheral interrupt flag status - Bridge D 0x20 32 read-write n 0x0 0x0 AC_ AC 4 1 ADC_ ADC 3 1 CCL_ CCL 7 1 EVSYS_ EVSYS 0 1 OPAMP_ OPAMP 6 1 PTC_ PTC 5 1 SERCOM5_ SERCOM5 1 1 TC4_ TC4 2 1 INTFLAGE Peripheral interrupt flag status - Bridge E 0x24 32 read-write n 0x0 0x0 DMAC_ DMAC 1 1 PAC_ PAC 0 1 STATUSA Peripheral write protection status - Bridge A 0x34 32 read-only n 0x0 0x0 EIC_ EIC APB Protect Enable 9 1 GCLK_ GCLK APB Protect Enable 6 1 MCLK_ MCLK APB Protect Enable 1 1 OSC32KCTRL_ OSC32KCTRL APB Protect Enable 4 1 OSCCTRL_ OSCCTRL APB Protect Enable 3 1 PM_ PM APB Protect Enable 0 1 PORT_ PORT APB Protect Enable 10 1 RSTC_ RSTC APB Protect Enable 2 1 RTC_ RTC APB Protect Enable 8 1 SUPC_ SUPC APB Protect Enable 5 1 TAL_ TAL APB Protect Enable 11 1 WDT_ WDT APB Protect Enable 7 1 STATUSB Peripheral write protection status - Bridge B 0x38 32 read-only n 0x0 0x0 DSU_ DSU APB Protect Enable 1 1 MTB_ MTB APB Protect Enable 3 1 NVMCTRL_ NVMCTRL APB Protect Enable 2 1 USB_ USB APB Protect Enable 0 1 STATUSC Peripheral write protection status - Bridge C 0x3C 32 read-only n 0x0 0x0 AES_ AES APB Protect Enable 13 1 DAC_ DAC APB Protect Enable 12 1 SERCOM0_ SERCOM0 APB Protect Enable 0 1 SERCOM1_ SERCOM1 APB Protect Enable 1 1 SERCOM2_ SERCOM2 APB Protect Enable 2 1 SERCOM3_ SERCOM3 APB Protect Enable 3 1 SERCOM4_ SERCOM4 APB Protect Enable 4 1 TC0_ TC0 APB Protect Enable 8 1 TC1_ TC1 APB Protect Enable 9 1 TCC0_ TCC0 APB Protect Enable 5 1 TCC1_ TCC1 APB Protect Enable 6 1 TCC2_ TCC2 APB Protect Enable 7 1 TRNG_ TRNG APB Protect Enable 14 1 STATUSD Peripheral write protection status - Bridge D 0x40 32 read-only n 0x0 0x0 AC_ AC APB Protect Enable 4 1 ADC_ ADC APB Protect Enable 3 1 CCL_ CCL APB Protect Enable 7 1 EVSYS_ EVSYS APB Protect Enable 0 1 OPAMP_ OPAMP APB Protect Enable 6 1 PTC_ PTC APB Protect Enable 5 1 SERCOM5_ SERCOM5 APB Protect Enable 1 1 TC4_ TC4 APB Protect Enable 2 1 STATUSE Peripheral write protection status - Bridge E 0x44 32 read-only n 0x0 0x0 DMAC_ DMAC APB Protect Enable 1 1 PAC_ PAC APB Protect Enable 0 1 WRCTRL Write control 0x0 32 read-write n 0x0 0x0 KEY Peripheral access control key 16 8 KEYSelect OFF No action 0x0 CLR Clear protection 0x1 SET Set protection 0x2 SETLCK Set and lock protection 0x3 PERID Peripheral identifier 0 16 PM Power Manager PM 0x0 0x0 0x2C registers n SYSTEM 0 CTRLA Control A 0x0 8 read-write n 0x0 0x0 IORET I/O Retention 2 1 INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 PLRDY Performance Level Interrupt Enable 0 1 write-only INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 PLRDY Performance Level Ready interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 PLRDY Performance Level Ready 0 1 PLCFG Performance Level Configuration 0x2 8 read-write n 0x0 0x0 PLDIS Performance Level Disable 7 1 PLSEL Performance Level Select 0 2 PLSELSelect PL0 Performance Level 0 0x0 PL1 Performance Level 1 0x1 PL2 Performance Level 2 0x2 PWSAKDLY Power Switch Acknowledge Delay 0xC 8 read-write n 0x0 0x0 DLYVAL Delay Value 0 7 IGNACK Ignore Acknowledge 7 1 SLEEPCFG Sleep Configuration 0x1 8 read-write n 0x0 0x0 SLEEPMODE Sleep Mode 0 3 SLEEPMODESelect IDLE0 CPU clock is OFF 0x0 IDLE1 AHB clock is OFF 0x1 IDLE2 APB clock are OFF 0x2 STANDBY All Clocks are OFF 0x4 BACKUP Only Backup domain is powered ON 0x5 OFF All power domains are powered OFF 0x6 STDBYCFG Standby Configuration 0x8 16 read-write n 0x0 0x0 BBIASHS Back Bias for HMCRAMCHS 10 2 BBIASLP Back Bias for HMCRAMCLP 12 2 BBIASPP Back Bias for PicoPram 14 2 DPGPD0 Dynamic Power Gating for PD0 4 1 DPGPD1 Dynamic Power Gating for PD1 5 1 LINKPD Linked Power Domain 8 2 LINKPDSelect DEFAULT Power domains are not linked 0x0 PD01 PD0 and PD1 power domains are linked 0x1 PD12 PD1 and PD2 power domains are linked 0x2 PD012 All power domains are linked 0x3 PDCFG Power Domain Configuration 0 2 PDCFGSelect DEFAULT All power domains switching is handled by hardware. 0x0 PD0 PD0 is forced ACTIVE. PD1 and PD2 power domains switching is handled by hardware. 0x1 PD01 PD0 and PD1 are forced ACTIVE. PD2 power domain switching is handled by hardware. 0x2 PD012 All power domains are forced ACTIVE. 0x3 VREGSMOD Voltage Regulator Standby mode 6 2 VREGSMODSelect AUTO Automatic mode 0x0 PERFORMANCE Performance oriented 0x1 LP Low Power oriented 0x2 PORT Port Module PORT 0x0 0x0 0x200 registers n CTRL0 Control 0x48 32 read-write n 0x0 0x0 SAMPLING Input Sampling Mode 0 32 write-only CTRL1 Control 0xEC 32 read-write n 0x0 0x0 SAMPLING Input Sampling Mode 0 32 write-only DIR0 Data Direction 0x0 32 read-write n 0x0 0x0 DIR1 Data Direction 0x80 32 read-write n 0x0 0x0 DIRCLR0 Data Direction Clear 0x8 32 read-write n 0x0 0x0 DIRCLR1 Data Direction Clear 0x8C 32 read-write n 0x0 0x0 DIRSET0 Data Direction Set 0x10 32 read-write n 0x0 0x0 DIRSET1 Data Direction Set 0x98 32 read-write n 0x0 0x0 DIRTGL0 Data Direction Toggle 0x18 32 read-write n 0x0 0x0 DIRTGL1 Data Direction Toggle 0xA4 32 read-write n 0x0 0x0 EVCTRL0 Event Input Control 0x58 32 read-write n 0x0 0x0 EVACT0 Port Event Action 0 5 2 EVACT1 Port Event Action 1 13 2 EVACT2 Port Event Action 2 21 2 EVACT3 Port Event Action 3 29 2 PID0 Port Event Pin Identifier 0 0 5 PID1 Port Event Pin Identifier 1 8 5 PID2 Port Event Pin Identifier 2 16 5 PID3 Port Event Pin Identifier 3 24 5 PORTEI0 Port Event Enable Input 0 7 1 PORTEI1 Port Event Enable Input 1 15 1 PORTEI2 Port Event Enable Input 2 23 1 PORTEI3 Port Event Enable Input 3 31 1 EVCTRL1 Event Input Control 0x104 32 read-write n 0x0 0x0 EVACT0 Port Event Action 0 5 2 EVACT1 Port Event Action 1 13 2 EVACT2 Port Event Action 2 21 2 EVACT3 Port Event Action 3 29 2 PID0 Port Event Pin Identifier 0 0 5 PID1 Port Event Pin Identifier 1 8 5 PID2 Port Event Pin Identifier 2 16 5 PID3 Port Event Pin Identifier 3 24 5 PORTEI0 Port Event Enable Input 0 7 1 PORTEI1 Port Event Enable Input 1 15 1 PORTEI2 Port Event Enable Input 2 23 1 PORTEI3 Port Event Enable Input 3 31 1 IN0 Data Input Value 0x40 32 read-only n 0x0 0x0 IN1 Data Input Value 0xE0 32 read-only n 0x0 0x0 OUT0 Data Output Value 0x20 32 read-write n 0x0 0x0 OUT1 Data Output Value 0xB0 32 read-write n 0x0 0x0 OUTCLR0 Data Output Value Clear 0x28 32 read-write n 0x0 0x0 OUTCLR1 Data Output Value Clear 0xBC 32 read-write n 0x0 0x0 OUTSET0 Data Output Value Set 0x30 32 read-write n 0x0 0x0 OUTSET1 Data Output Value Set 0xC8 32 read-write n 0x0 0x0 OUTTGL0 Data Output Value Toggle 0x38 32 read-write n 0x0 0x0 OUTTGL1 Data Output Value Toggle 0xD4 32 read-write n 0x0 0x0 PINCFG0_0 Pin Configuration n - Group 0 0x80 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_1 Pin Configuration n - Group 0 0xC1 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_10 Pin Configuration n - Group 0 0x337 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_11 Pin Configuration n - Group 0 0x382 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_12 Pin Configuration n - Group 0 0x3CE 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_13 Pin Configuration n - Group 0 0x41B 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_14 Pin Configuration n - Group 0 0x469 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_15 Pin Configuration n - Group 0 0x4B8 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_16 Pin Configuration n - Group 0 0x508 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_17 Pin Configuration n - Group 0 0x559 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_18 Pin Configuration n - Group 0 0x5AB 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_19 Pin Configuration n - Group 0 0x5FE 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_2 Pin Configuration n - Group 0 0x103 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_20 Pin Configuration n - Group 0 0x652 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_21 Pin Configuration n - Group 0 0x6A7 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_22 Pin Configuration n - Group 0 0x6FD 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_23 Pin Configuration n - Group 0 0x754 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_24 Pin Configuration n - Group 0 0x7AC 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_25 Pin Configuration n - Group 0 0x805 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_26 Pin Configuration n - Group 0 0x85F 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_27 Pin Configuration n - Group 0 0x8BA 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_28 Pin Configuration n - Group 0 0x916 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_29 Pin Configuration n - Group 0 0x973 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_3 Pin Configuration n - Group 0 0x146 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_30 Pin Configuration n - Group 0 0x9D1 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_31 Pin Configuration n - Group 0 0xA30 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_4 Pin Configuration n - Group 0 0x18A 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_5 Pin Configuration n - Group 0 0x1CF 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_6 Pin Configuration n - Group 0 0x215 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_7 Pin Configuration n - Group 0 0x25C 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_8 Pin Configuration n - Group 0 0x2A4 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_9 Pin Configuration n - Group 0 0x2ED 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG1_0 Pin Configuration n - Group 1 0x180 read-write n 0x0 0x0 PINCFG1_1 Pin Configuration n - Group 1 0x241 read-write n 0x0 0x0 PINCFG1_10 Pin Configuration n - Group 1 0x937 read-write n 0x0 0x0 PINCFG1_11 Pin Configuration n - Group 1 0xA02 read-write n 0x0 0x0 PINCFG1_12 Pin Configuration n - Group 1 0xACE read-write n 0x0 0x0 PINCFG1_13 Pin Configuration n - Group 1 0xB9B read-write n 0x0 0x0 PINCFG1_14 Pin Configuration n - Group 1 0xC69 read-write n 0x0 0x0 PINCFG1_15 Pin Configuration n - Group 1 0xD38 read-write n 0x0 0x0 PINCFG1_16 Pin Configuration n - Group 1 0xE08 read-write n 0x0 0x0 PINCFG1_17 Pin Configuration n - Group 1 0xED9 read-write n 0x0 0x0 PINCFG1_18 Pin Configuration n - Group 1 0xFAB read-write n 0x0 0x0 PINCFG1_19 Pin Configuration n - Group 1 0x107E read-write n 0x0 0x0 PINCFG1_2 Pin Configuration n - Group 1 0x303 read-write n 0x0 0x0 PINCFG1_20 Pin Configuration n - Group 1 0x1152 read-write n 0x0 0x0 PINCFG1_21 Pin Configuration n - Group 1 0x1227 read-write n 0x0 0x0 PINCFG1_22 Pin Configuration n - Group 1 0x12FD read-write n 0x0 0x0 PINCFG1_23 Pin Configuration n - Group 1 0x13D4 read-write n 0x0 0x0 PINCFG1_24 Pin Configuration n - Group 1 0x14AC read-write n 0x0 0x0 PINCFG1_25 Pin Configuration n - Group 1 0x1585 read-write n 0x0 0x0 PINCFG1_26 Pin Configuration n - Group 1 0x165F read-write n 0x0 0x0 PINCFG1_27 Pin Configuration n - Group 1 0x173A read-write n 0x0 0x0 PINCFG1_28 Pin Configuration n - Group 1 0x1816 read-write n 0x0 0x0 PINCFG1_29 Pin Configuration n - Group 1 0x18F3 read-write n 0x0 0x0 PINCFG1_3 Pin Configuration n - Group 1 0x3C6 read-write n 0x0 0x0 PINCFG1_30 Pin Configuration n - Group 1 0x19D1 read-write n 0x0 0x0 PINCFG1_31 Pin Configuration n - Group 1 0x1AB0 read-write n 0x0 0x0 PINCFG1_4 Pin Configuration n - Group 1 0x48A read-write n 0x0 0x0 PINCFG1_5 Pin Configuration n - Group 1 0x54F read-write n 0x0 0x0 PINCFG1_6 Pin Configuration n - Group 1 0x615 read-write n 0x0 0x0 PINCFG1_7 Pin Configuration n - Group 1 0x6DC read-write n 0x0 0x0 PINCFG1_8 Pin Configuration n - Group 1 0x7A4 read-write n 0x0 0x0 PINCFG1_9 Pin Configuration n - Group 1 0x86D read-write n 0x0 0x0 PMUX0_0 Peripheral Multiplexing n - Group 0 0x60 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_1 Peripheral Multiplexing n - Group 0 0x91 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_10 Peripheral Multiplexing n - Group 0 0x277 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_11 Peripheral Multiplexing n - Group 0 0x2B2 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_12 Peripheral Multiplexing n - Group 0 0x2EE 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_13 Peripheral Multiplexing n - Group 0 0x32B 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_14 Peripheral Multiplexing n - Group 0 0x369 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_15 Peripheral Multiplexing n - Group 0 0x3A8 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_2 Peripheral Multiplexing n - Group 0 0xC3 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_3 Peripheral Multiplexing n - Group 0 0xF6 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_4 Peripheral Multiplexing n - Group 0 0x12A 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_5 Peripheral Multiplexing n - Group 0 0x15F 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_6 Peripheral Multiplexing n - Group 0 0x195 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_7 Peripheral Multiplexing n - Group 0 0x1CC 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_8 Peripheral Multiplexing n - Group 0 0x204 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_9 Peripheral Multiplexing n - Group 0 0x23D 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX1_0 Peripheral Multiplexing n - Group 1 0x160 read-write n 0x0 0x0 PMUX1_1 Peripheral Multiplexing n - Group 1 0x211 read-write n 0x0 0x0 PMUX1_10 Peripheral Multiplexing n - Group 1 0x877 read-write n 0x0 0x0 PMUX1_11 Peripheral Multiplexing n - Group 1 0x932 read-write n 0x0 0x0 PMUX1_12 Peripheral Multiplexing n - Group 1 0x9EE read-write n 0x0 0x0 PMUX1_13 Peripheral Multiplexing n - Group 1 0xAAB read-write n 0x0 0x0 PMUX1_14 Peripheral Multiplexing n - Group 1 0xB69 read-write n 0x0 0x0 PMUX1_15 Peripheral Multiplexing n - Group 1 0xC28 read-write n 0x0 0x0 PMUX1_2 Peripheral Multiplexing n - Group 1 0x2C3 read-write n 0x0 0x0 PMUX1_3 Peripheral Multiplexing n - Group 1 0x376 read-write n 0x0 0x0 PMUX1_4 Peripheral Multiplexing n - Group 1 0x42A read-write n 0x0 0x0 PMUX1_5 Peripheral Multiplexing n - Group 1 0x4DF read-write n 0x0 0x0 PMUX1_6 Peripheral Multiplexing n - Group 1 0x595 read-write n 0x0 0x0 PMUX1_7 Peripheral Multiplexing n - Group 1 0x64C read-write n 0x0 0x0 PMUX1_8 Peripheral Multiplexing n - Group 1 0x704 read-write n 0x0 0x0 PMUX1_9 Peripheral Multiplexing n - Group 1 0x7BD read-write n 0x0 0x0 WRCONFIG0 Write Configuration 0x50 32 write-only n 0x0 0x0 DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing Template 24 4 PMUXEN Select Peripheral Multiplexer 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG Registers 30 1 WRPMUX Write PMUX Registers 28 1 WRCONFIG1 Write Configuration 0xF8 32 write-only n 0x0 0x0 DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing Template 24 4 PMUXEN Select Peripheral Multiplexer 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG Registers 30 1 WRPMUX Write PMUX Registers 28 1 RSTC Reset Controller RSTC 0x0 0x0 0x20 registers n BKUPEXIT Backup Exit Source 0x2 8 read-only n 0x0 0x0 BBPS Battery Backup Power Switch 2 1 read-only EXTWAKE External Wakeup 0 1 read-only RTC Real Timer Counter Interrupt 1 1 read-only RCAUSE Reset Cause 0x0 8 read-only n 0x0 0x0 BACKUP Backup Reset 7 1 BOD12 Brown Out 12 Detector Reset 1 1 BOD33 Brown Out 33 Detector Reset 2 1 EXT External Reset 4 1 POR Power On Reset 0 1 SYST System Reset Request 6 1 WDT Watchdog Reset 5 1 WKCAUSE Wakeup Cause 0x10 16 read-write n 0x0 0x0 WKCAUSE Wakeup Cause 0 16 read-only WKDBCONF Wakeup Debounce Configuration 0x4 8 read-write n 0x0 0x0 WKDBCNT Wakeup Debounce Counter 0 5 WKDBCNTSelect OFF No debouncing.Input pin is low or high level sensitive depending on its WKPOLx bit. 0x0 2CK32 Input pin shall be active for at least two 32kHz clock period. 0x1 3CK32 Input pin shall be active for at least three 32kHz clock period. 0x2 32CK32 Input pin shall be active for at least 32 32kHz clock period. 0x3 512CK32 Input pin shall be active for at least 512 32kHz clock period. 0x4 4096CK32 Input pin shall be active for at least 4096 32kHz clock period. 0x5 32768CK32 Input pin shall be active for at least 32768 32kHz clock period. 0x6 WKEN Wakeup Enable 0xC 16 read-write n 0x0 0x0 WKEN Wakeup Enable 0 8 WKPOL Wakeup Polarity 0x8 16 read-write n 0x0 0x0 WKPOL Wakeup Polarity 0 8 RTC Real-Time Counter RTC 0x0 0x0 0x2C registers n RTC 2 ALARM1 MODE2 Alarm n Value 0x20 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 CLOCK MODE2 Clock Value 0x18 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 COMP0 MODE1 Compare n Value 0x20 16 read-write n 0x0 0x0 COMP Compare Value 0 16 COMP1 MODE1 Compare n Value 0x22 16 read-write n 0x0 0x0 COMP Compare Value 0 16 COUNT MODE1 Counter Value 0x18 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 CTRLA MODE2 Control A 0x0 16 read-write n 0x0 0x0 CLKREP Clock Representation 6 1 CLOCKSYNC Clock Read Synchronization Enable 15 1 COUNTSYNC Count Read Synchronization Enable 15 1 ENABLE Enable 1 1 MATCHCLR Clear on Match 7 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xa DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xb SWRST Software Reset 0 1 write-only DBGCTRL Debug Control 0xE 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 EVCTRL MODE2 Event Control 0x4 32 read-write n 0x0 0x0 ALARMEO0 Alarm 0 Event Output Enable 8 1 CMPEO0 Compare 0 Event Output Enable 8 1 CMPEO1 Compare 1 Event Output Enable 9 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 FREQCORR Frequency Correction 0x14 8 read-write n 0x0 0x0 SIGN Correction Sign 7 1 VALUE Correction Value 0 7 GP0 General Purpose 0x40 32 read-write n 0x0 0x0 GP1 General Purpose 0x44 32 read-write n 0x0 0x0 GP2 General Purpose 0x48 32 read-write n 0x0 0x0 GP3 General Purpose 0x4C 32 read-write n 0x0 0x0 INTENCLR MODE2 Interrupt Enable Clear 0x8 16 read-write n 0x0 0x0 ALARM0 Alarm 0 Interrupt Enable 8 1 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 write-only PER1 Periodic Interval 1 Interrupt Enable 1 1 write-only PER2 Periodic Interval 2 Interrupt Enable 2 1 write-only PER3 Periodic Interval 3 Interrupt Enable 3 1 write-only PER4 Periodic Interval 4 Interrupt Enable 4 1 write-only PER5 Periodic Interval 5 Interrupt Enable 5 1 write-only PER6 Periodic Interval 6 Interrupt Enable 6 1 write-only PER7 Periodic Interval 7 Interrupt Enable 7 1 write-only INTENSET MODE2 Interrupt Enable Set 0xA 16 read-write n 0x0 0x0 ALARM0 Alarm 0 Interrupt Enable 8 1 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Enable 0 1 PER1 Periodic Interval 1 Enable 1 1 PER2 Periodic Interval 2 Enable 2 1 PER3 Periodic Interval 3 Enable 3 1 PER4 Periodic Interval 4 Enable 4 1 PER5 Periodic Interval 5 Enable 5 1 PER6 Periodic Interval 6 Enable 6 1 PER7 Periodic Interval 7 Enable 7 1 INTFLAG MODE2 Interrupt Flag Status and Clear 0xC 16 read-write n 0x0 0x0 ALARM0 Alarm 0 8 1 CMP0 Compare 0 8 1 CMP1 Compare 1 9 1 OVF Overflow 15 1 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 MASK1 MODE2 Alarm n Mask 0x24 8 read-write n 0x0 0x0 SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0x0 SS Match seconds only 0x1 MMSS Match seconds and minutes only 0x2 HHMMSS Match seconds, minutes, and hours only 0x3 DDHHMMSS Match seconds, minutes, hours, and days only 0x4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x6 MODE0 - COMP0 32-bit Counter with Single 32-bit Compare - - MODE0 Compare n Value 0x40 32 read-write n 0x0 0x0 COMP Compare Value 0 32 MODE0 - COUNT 32-bit Counter with Single 32-bit Compare - - MODE0 Counter Value 0x18 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 MODE0 - CTRLA 32-bit Counter with Single 32-bit Compare - - MODE0 Control A 0x0 16 read-write n 0x0 0x0 COUNTSYNC Count Read Synchronization Enable 15 1 ENABLE Enable 1 1 MATCHCLR Clear on Match 7 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xa DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xb SWRST Software Reset 0 1 write-only MODE0 - DBGCTRL 32-bit Counter with Single 32-bit Compare - - Debug Control 0xE 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 MODE0 - EVCTRL 32-bit Counter with Single 32-bit Compare - - MODE0 Event Control 0x4 32 read-write n 0x0 0x0 CMPEO0 Compare 0 Event Output Enable 8 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 MODE0 - FREQCORR 32-bit Counter with Single 32-bit Compare - - Frequency Correction 0x14 8 read-write n 0x0 0x0 SIGN Correction Sign 7 1 VALUE Correction Value 0 7 MODE0 - GP0 32-bit Counter with Single 32-bit Compare - - General Purpose 0x80 32 read-write n 0x0 0x0 MODE0 - GP1 32-bit Counter with Single 32-bit Compare - - General Purpose 0xC4 32 read-write n 0x0 0x0 MODE0 - GP2 32-bit Counter with Single 32-bit Compare - - General Purpose 0x10C 32 read-write n 0x0 0x0 MODE0 - GP3 32-bit Counter with Single 32-bit Compare - - General Purpose 0x158 32 read-write n 0x0 0x0 MODE0 - INTENCLR 32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Enable Clear 0x8 16 read-write n 0x0 0x0 CMP0 Compare 0 Interrupt Enable 8 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 write-only PER1 Periodic Interval 1 Interrupt Enable 1 1 write-only PER2 Periodic Interval 2 Interrupt Enable 2 1 write-only PER3 Periodic Interval 3 Interrupt Enable 3 1 write-only PER4 Periodic Interval 4 Interrupt Enable 4 1 write-only PER5 Periodic Interval 5 Interrupt Enable 5 1 write-only PER6 Periodic Interval 6 Interrupt Enable 6 1 write-only PER7 Periodic Interval 7 Interrupt Enable 7 1 write-only MODE0 - INTENSET 32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Enable Set 0xA 16 read-write n 0x0 0x0 CMP0 Compare 0 Interrupt Enable 8 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 MODE0 - INTFLAG 32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Flag Status and Clear 0xC 16 read-write n 0x0 0x0 CMP0 Compare 0 8 1 OVF Overflow 15 1 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 MODE0 - SYNCBUSY 32-bit Counter with Single 32-bit Compare - - MODE0 Synchronization Busy Status 0x10 32 read-only n 0x0 0x0 COMP0 COMP 0 Register Busy 5 1 read-only COUNT COUNT Register Busy 3 1 read-only COUNTSYNC Count Read Synchronization Enable Bit Busy 15 1 read-only ENABLE Enable Bit Busy 1 1 read-only FREQCORR FREQCORR Register Busy 2 1 read-only SWRST Software Reset Busy 0 1 read-only MODE1 - COMP0 16-bit Counter with Two 16-bit Compares - - MODE1 Compare n Value 0x40 16 read-write n 0x0 0x0 COMP Compare Value 0 16 MODE1 - COMP1 16-bit Counter with Two 16-bit Compares - - MODE1 Compare n Value 0x62 16 read-write n 0x0 0x0 COMP Compare Value 0 16 MODE1 - COUNT 16-bit Counter with Two 16-bit Compares - - MODE1 Counter Value 0x18 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 MODE1 - CTRLA 16-bit Counter with Two 16-bit Compares - - MODE1 Control A 0x0 16 read-write n 0x0 0x0 COUNTSYNC Count Read Synchronization Enable 15 1 ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xa DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xb SWRST Software Reset 0 1 write-only MODE1 - DBGCTRL 16-bit Counter with Two 16-bit Compares - - Debug Control 0xE 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 MODE1 - EVCTRL 16-bit Counter with Two 16-bit Compares - - MODE1 Event Control 0x4 32 read-write n 0x0 0x0 CMPEO0 Compare 0 Event Output Enable 8 1 CMPEO1 Compare 1 Event Output Enable 9 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 MODE1 - FREQCORR 16-bit Counter with Two 16-bit Compares - - Frequency Correction 0x14 8 read-write n 0x0 0x0 SIGN Correction Sign 7 1 VALUE Correction Value 0 7 MODE1 - GP0 16-bit Counter with Two 16-bit Compares - - General Purpose 0x80 32 read-write n 0x0 0x0 MODE1 - GP1 16-bit Counter with Two 16-bit Compares - - General Purpose 0xC4 32 read-write n 0x0 0x0 MODE1 - GP2 16-bit Counter with Two 16-bit Compares - - General Purpose 0x10C 32 read-write n 0x0 0x0 MODE1 - GP3 16-bit Counter with Two 16-bit Compares - - General Purpose 0x158 32 read-write n 0x0 0x0 MODE1 - INTENCLR 16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Enable Clear 0x8 16 read-write n 0x0 0x0 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 MODE1 - INTENSET 16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Enable Set 0xA 16 read-write n 0x0 0x0 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 MODE1 - INTFLAG 16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Flag Status and Clear 0xC 16 read-write n 0x0 0x0 CMP0 Compare 0 8 1 CMP1 Compare 1 9 1 OVF Overflow 15 1 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 MODE1 - PER 16-bit Counter with Two 16-bit Compares - - MODE1 Counter Period 0x1C 16 read-write n 0x0 0x0 PER Counter Period 0 16 MODE1 - SYNCBUSY 16-bit Counter with Two 16-bit Compares - - MODE1 Synchronization Busy Status 0x10 32 read-only n 0x0 0x0 COMP0 COMP 0 Register Busy 5 1 read-only COMP1 COMP 1 Register Busy 6 1 read-only COUNT COUNT Register Busy 3 1 read-only COUNTSYNC Count Read Synchronization Enable Bit Busy 15 1 read-only ENABLE Enable Bit Busy 1 1 read-only FREQCORR FREQCORR Register Busy 2 1 read-only PER PER Register Busy 4 1 read-only SWRST Software Reset Bit Busy 0 1 read-only MODE2 - ALARM0 Clock/Calendar with Alarm - - MODE2 Alarm n Value 0x40 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 MODE2 - CLOCK Clock/Calendar with Alarm - - MODE2 Clock Value 0x18 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 MODE2 - CTRLA Clock/Calendar with Alarm - - MODE2 Control A 0x0 16 read-write n 0x0 0x0 CLKREP Clock Representation 6 1 CLOCKSYNC Clock Read Synchronization Enable 15 1 ENABLE Enable 1 1 MATCHCLR Clear on Match 7 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xa DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xb SWRST Software Reset 0 1 write-only MODE2 - DBGCTRL Clock/Calendar with Alarm - - Debug Control 0xE 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 MODE2 - EVCTRL Clock/Calendar with Alarm - - MODE2 Event Control 0x4 32 read-write n 0x0 0x0 ALARMEO0 Alarm 0 Event Output Enable 8 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 MODE2 - FREQCORR Clock/Calendar with Alarm - - Frequency Correction 0x14 8 read-write n 0x0 0x0 SIGN Correction Sign 7 1 VALUE Correction Value 0 7 MODE2 - GP0 Clock/Calendar with Alarm - - General Purpose 0x80 32 read-write n 0x0 0x0 MODE2 - GP1 Clock/Calendar with Alarm - - General Purpose 0xC4 32 read-write n 0x0 0x0 MODE2 - GP2 Clock/Calendar with Alarm - - General Purpose 0x10C 32 read-write n 0x0 0x0 MODE2 - GP3 Clock/Calendar with Alarm - - General Purpose 0x158 32 read-write n 0x0 0x0 MODE2 - INTENCLR Clock/Calendar with Alarm - - MODE2 Interrupt Enable Clear 0x8 16 read-write n 0x0 0x0 ALARM0 Alarm 0 Interrupt Enable 8 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 MODE2 - INTENSET Clock/Calendar with Alarm - - MODE2 Interrupt Enable Set 0xA 16 read-write n 0x0 0x0 ALARM0 Alarm 0 Interrupt Enable 8 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Enable 0 1 PER1 Periodic Interval 1 Enable 1 1 PER2 Periodic Interval 2 Enable 2 1 PER3 Periodic Interval 3 Enable 3 1 PER4 Periodic Interval 4 Enable 4 1 PER5 Periodic Interval 5 Enable 5 1 PER6 Periodic Interval 6 Enable 6 1 PER7 Periodic Interval 7 Enable 7 1 MODE2 - INTFLAG Clock/Calendar with Alarm - - MODE2 Interrupt Flag Status and Clear 0xC 16 read-write n 0x0 0x0 ALARM0 Alarm 0 8 1 OVF Overflow 15 1 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 MODE2 - MASK0 Clock/Calendar with Alarm - - MODE2 Alarm n Mask 0x48 8 read-write n 0x0 0x0 SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0x0 SS Match seconds only 0x1 MMSS Match seconds and minutes only 0x2 HHMMSS Match seconds, minutes, and hours only 0x3 DDHHMMSS Match seconds, minutes, hours, and days only 0x4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x6 MODE2 - SYNCBUSY Clock/Calendar with Alarm - - MODE2 Synchronization Busy Status 0x10 32 read-only n 0x0 0x0 ALARM0 ALARM 0 Register Busy 5 1 read-only CLOCK CLOCK Register Busy 3 1 read-only CLOCKSYNC Clock Read Synchronization Enable Bit Busy 15 1 read-only ENABLE Enable Bit Busy 1 1 read-only FREQCORR FREQCORR Register Busy 2 1 read-only MASK0 MASK 0 Register Busy 11 1 read-only SWRST Software Reset Bit Busy 0 1 read-only PER MODE1 Counter Period 0x1C 16 read-write n 0x0 0x0 PER Counter Period 0 16 SYNCBUSY MODE2 Synchronization Busy Status 0x10 32 read-only n 0x0 0x0 ALARM0 ALARM 0 Register Busy 5 1 read-only CLOCK CLOCK Register Busy 3 1 read-only CLOCKSYNC Clock Read Synchronization Enable Bit Busy 15 1 read-only COMP0 COMP 0 Register Busy 5 1 read-only COMP1 COMP 1 Register Busy 6 1 read-only COUNT COUNT Register Busy 3 1 read-only COUNTSYNC Count Read Synchronization Enable Bit Busy 15 1 read-only ENABLE Enable Bit Busy 1 1 read-only FREQCORR FREQCORR Register Busy 2 1 read-only MASK0 MASK 0 Register Busy 11 1 read-only PER PER Register Busy 4 1 read-only SWRST Software Reset Bit Busy 0 1 read-only SERCOM0 Serial Communication Interface 0 SERCOM 0x0 0x0 0x40 registers n SERCOM0 8 ADDR SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 FP Fractional Part 13 3 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 CTRLA USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 CTRLB USART Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 DATA USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 DBGCTRL USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate DEFAULT_MODE 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only DIR Read/Write Direction 3 1 read-only FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SYNCBUSY USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM1 Serial Communication Interface 1 SERCOM 0x0 0x0 0x40 registers n SERCOM1 9 ADDR SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 FP Fractional Part 13 3 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 CTRLA USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 CTRLB USART Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 DATA USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 DBGCTRL USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate DEFAULT_MODE 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only DIR Read/Write Direction 3 1 read-only FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SYNCBUSY USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM2 Serial Communication Interface 2 SERCOM 0x0 0x0 0x40 registers n SERCOM2 10 ADDR SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 FP Fractional Part 13 3 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 CTRLA USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 CTRLB USART Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 DATA USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 DBGCTRL USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate DEFAULT_MODE 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only DIR Read/Write Direction 3 1 read-only FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SYNCBUSY USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM3 Serial Communication Interface 3 SERCOM 0x0 0x0 0x40 registers n SERCOM3 11 ADDR SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 FP Fractional Part 13 3 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 CTRLA USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 CTRLB USART Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 DATA USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 DBGCTRL USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate DEFAULT_MODE 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only DIR Read/Write Direction 3 1 read-only FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SYNCBUSY USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM4 Serial Communication Interface 4 SERCOM 0x0 0x0 0x40 registers n SERCOM4 12 ADDR SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 FP Fractional Part 13 3 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 CTRLA USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 CTRLB USART Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 DATA USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 DBGCTRL USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate DEFAULT_MODE 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only DIR Read/Write Direction 3 1 read-only FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SYNCBUSY USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM5 Serial Communication Interface 5 SERCOM 0x0 0x0 0x40 registers n SERCOM5 13 ADDR SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 FP Fractional Part 13 3 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 CTRLA USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 CTRLB USART Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 DATA USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 DBGCTRL USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate DEFAULT_MODE 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only DIR Read/Write Direction 3 1 read-only FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SYNCBUSY USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SUPC Supply Controller SUPC 0x0 0x0 0x2C registers n SYSTEM 0 BBPS Battery Backup Power Switch 0x20 32 read-write n 0x0 0x0 CONF Battery Backup Configuration 0 2 CONFSelect NONE The backup domain is always supplied by main power 0x0 APWS The power switch is handled by the automatic power switch 0x1 FORCED The backup domain is always supplied by battery backup power 0x2 BOD33 The power switch is handled by the BOD33 0x3 PSOKEN Power Supply OK Enable 3 1 WAKEEN Wake Enable 2 1 BKIN Backup Input Control 0x28 32 read-only n 0x0 0x0 BKIN Backup Input Value 0 8 read-only BKOUT Backup Output Control 0x24 32 read-write n 0x0 0x0 CLR Clear Output 8 2 write-only EN Enable Output 0 2 RTCTGL RTC Toggle Output 24 2 SET Set Output 16 2 write-only BOD12 BOD12 Control 0x14 32 read-write n 0x0 0x0 ACTCFG Configuration in Active mode 8 1 ACTION Action when Threshold Crossed 3 2 ACTIONSelect NONE No action 0x0 RESET The BOD12 generates a reset 0x1 INT The BOD12 generates an interrupt 0x2 ENABLE Enable 1 1 HYST Hysteresis Enable 2 1 LEVEL Threshold Level 16 6 PSEL Prescaler Select 12 4 PSELSelect DIV2 Divide clock by 2 0x0 DIV4 Divide clock by 4 0x1 DIV8 Divide clock by 8 0x2 DIV16 Divide clock by 16 0x3 DIV32 Divide clock by 32 0x4 DIV64 Divide clock by 64 0x5 DIV128 Divide clock by 128 0x6 DIV256 Divide clock by 256 0x7 DIV512 Divide clock by 512 0x8 DIV1024 Divide clock by 1024 0x9 DIV2048 Divide clock by 2048 0xa DIV4096 Divide clock by 4096 0xb DIV8192 Divide clock by 8192 0xc DIV16384 Divide clock by 16384 0xd DIV32768 Divide clock by 32768 0xe DIV65536 Divide clock by 65536 0xf RUNSTDBY Run during Standby 6 1 STDBYCFG Configuration in Standby mode 5 1 BOD33 BOD33 Control 0x10 32 read-write n 0x0 0x0 ACTCFG Configuration in Active mode 8 1 ACTION Action when Threshold Crossed 3 2 ACTIONSelect NONE No action 0x0 RESET The BOD33 generates a reset 0x1 INT The BOD33 generates an interrupt 0x2 BKUP The BOD33 puts the device in backup sleep mode if VMON=0 0x3 BKUPLEVEL Threshold Level in backup sleep mode or for VBAT 24 6 ENABLE Enable 1 1 HYST Hysteresis Enable 2 1 LEVEL Threshold Level for VDD 16 6 PSEL Prescaler Select 12 4 PSELSelect DIV2 Divide clock by 2 0x0 DIV4 Divide clock by 4 0x1 DIV8 Divide clock by 8 0x2 DIV16 Divide clock by 16 0x3 DIV32 Divide clock by 32 0x4 DIV64 Divide clock by 64 0x5 DIV128 Divide clock by 128 0x6 DIV256 Divide clock by 256 0x7 DIV512 Divide clock by 512 0x8 DIV1024 Divide clock by 1024 0x9 DIV2048 Divide clock by 2048 0xa DIV4096 Divide clock by 4096 0xb DIV8192 Divide clock by 8192 0xc DIV16384 Divide clock by 16384 0xd DIV32768 Divide clock by 32768 0xe DIV65536 Divide clock by 65536 0xf RUNBKUP Configuration in Backup mode 7 1 RUNSTDBY Run during Standby 6 1 STDBYCFG Configuration in Standby mode 5 1 VMON Voltage Monitored in active and standby mode 10 1 INTENCLR Interrupt Enable Clear 0x0 32 read-write n 0x0 0x0 APWSRDY Automatic Power Switch Ready 9 1 B12SRDY BOD12 Synchronization Ready 5 1 B33SRDY BOD33 Synchronization Ready 2 1 BOD12DET BOD12 Detection 4 1 BOD12RDY BOD12 Ready 3 1 BOD33DET BOD33 Detection 1 1 BOD33RDY BOD33 Ready 0 1 VCORERDY VDDCORE Ready 10 1 VREGRDY Voltage Regulator Ready 8 1 INTENSET Interrupt Enable Set 0x4 32 read-write n 0x0 0x0 APWSRDY Automatic Power Switch Ready 9 1 B12SRDY BOD12 Synchronization Ready 5 1 B33SRDY BOD33 Synchronization Ready 2 1 BOD12DET BOD12 Detection 4 1 BOD12RDY BOD12 Ready 3 1 BOD33DET BOD33 Detection 1 1 BOD33RDY BOD33 Ready 0 1 VCORERDY VDDCORE Ready 10 1 VREGRDY Voltage Regulator Ready 8 1 INTFLAG Interrupt Flag Status and Clear 0x8 32 read-write n 0x0 0x0 APWSRDY Automatic Power Switch Ready 9 1 B12SRDY BOD12 Synchronization Ready 5 1 B33SRDY BOD33 Synchronization Ready 2 1 BOD12DET BOD12 Detection 4 1 BOD12RDY BOD12 Ready 3 1 BOD33DET BOD33 Detection 1 1 BOD33RDY BOD33 Ready 0 1 VCORERDY VDDCORE Ready 10 1 VREGRDY Voltage Regulator Ready 8 1 STATUS Power and Clocks Status 0xC 32 read-only n 0x0 0x0 APWSRDY Automatic Power Switch Ready 9 1 read-only B12SRDY BOD12 Synchronization Ready 5 1 read-only B33SRDY BOD33 Synchronization Ready 2 1 read-only BBPS Battery Backup Power Switch 11 1 read-only BOD12DET BOD12 Detection 4 1 read-only BOD12RDY BOD12 Ready 3 1 read-only BOD33DET BOD33 Detection 1 1 read-only BOD33RDY BOD33 Ready 0 1 read-only VCORERDY VDDCORE Ready 10 1 read-only VREGRDY Voltage Regulator Ready 8 1 read-only VREF VREF Control 0x1C 32 read-write n 0x0 0x0 ONDEMAND On Demand Contrl 7 1 RUNSTDBY Run during Standby 6 1 SEL Voltage Reference Selection 16 4 SELSelect 1V0 1.0V voltage reference typical value 0x0 1V1 1.1V voltage reference typical value 0x1 1V2 1.2V voltage reference typical value 0x2 1V25 1.25V voltage reference typical value 0x3 2V0 2.0V voltage reference typical value 0x4 2V2 2.2V voltage reference typical value 0x5 2V4 2.4V voltage reference typical value 0x6 2V5 2.5V voltage reference typical value 0x7 TSEN Temperature Sensor Output Enable 1 1 VREFOE Voltage Reference Output Enable 2 1 VREG VREG Control 0x18 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LPEFF Low Power Efficiency 8 1 RUNSTDBY Run during Standby 6 1 SEL Voltage Regulator Selection in active mode 2 2 SELSelect LDO LDO selection 0x0 BUCK Buck selection 0x1 SCVREG Switched Cap selection 0x2 VSPER Voltage Scaling Period 24 8 VSVSTEP Voltage Scaling Voltage Step 16 4 TAL Trigger Allocator TAL 0x0 0x0 0x2C registers n SYSTEM 0 BRKSTATUS Break Request Status 0xE 16 read-only n 0x0 0x0 CM0P CM0P Break Request 0 2 EVBRK Event Break Request 12 2 EXTBRK External Break Request 14 2 PPP PPP Break Request 2 2 CTICTRLA0 Cross-Trigger Interface n Control A 0x20 8 read-write n 0x0 0x0 ACTION Action when global break issued 0 2 ACTIONSelect BREAK Break when requested 0x0 INTERRUPT Trigger DBG interrupt instead of break 0x1 IGNORE Ignore break request 0x2 RESTART Action when global restart issued 2 1 CTICTRLA1 Cross-Trigger Interface n Control A 0x32 8 read-write n 0x0 0x0 ACTION Action when global break issued 0 2 ACTIONSelect BREAK Break when requested 0x0 INTERRUPT Trigger DBG interrupt instead of break 0x1 IGNORE Ignore break request 0x2 RESTART Action when global restart issued 2 1 CTICTRLA2 Cross-Trigger Interface n Control A 0x46 8 read-write n 0x0 0x0 ACTION Action when global break issued 0 2 ACTIONSelect BREAK Break when requested 0x0 INTERRUPT Trigger DBG interrupt instead of break 0x1 IGNORE Ignore break request 0x2 RESTART Action when global restart issued 2 1 CTICTRLA3 Cross-Trigger Interface n Control A 0x5C 8 read-write n 0x0 0x0 ACTION Action when global break issued 0 2 ACTIONSelect BREAK Break when requested 0x0 INTERRUPT Trigger DBG interrupt instead of break 0x1 IGNORE Ignore break request 0x2 RESTART Action when global restart issued 2 1 CTIMASK0 Cross-Trigger Interface n Mask 0x22 8 read-write n 0x0 0x0 CM0P CM0P Break Master 0 1 EVBRK Event Break Master 6 1 EXTBRK External Break Master 7 1 PPP PPP Break Master 1 1 CTIMASK1 Cross-Trigger Interface n Mask 0x35 8 read-write n 0x0 0x0 CM0P CM0P Break Master 0 1 EVBRK Event Break Master 6 1 EXTBRK External Break Master 7 1 PPP PPP Break Master 1 1 CTIMASK2 Cross-Trigger Interface n Mask 0x4A 8 read-write n 0x0 0x0 CM0P CM0P Break Master 0 1 EVBRK Event Break Master 6 1 EXTBRK External Break Master 7 1 PPP PPP Break Master 1 1 CTIMASK3 Cross-Trigger Interface n Mask 0x61 8 read-write n 0x0 0x0 CM0P CM0P Break Master 0 1 EVBRK Event Break Master 6 1 EXTBRK External Break Master 7 1 PPP PPP Break Master 1 1 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 SWRST Software Reset 0 1 DMACPUSEL0 DMA Channel Interrupts CPU Select 0 0x40 32 read-write n 0x0 0x0 CH0 DMA Channel 0 Interrupt CPU Select 0 1 CH1 DMA Channel 1 Interrupt CPU Select 2 1 CH10 DMA Channel 10 Interrupt CPU Select 20 1 CH11 DMA Channel 11 Interrupt CPU Select 22 1 CH12 DMA Channel 12 Interrupt CPU Select 24 1 CH13 DMA Channel 13 Interrupt CPU Select 26 1 CH14 DMA Channel 14 Interrupt CPU Select 28 1 CH15 DMA Channel 15 Interrupt CPU Select 30 1 CH2 DMA Channel 2 Interrupt CPU Select 4 1 CH3 DMA Channel 3 Interrupt CPU Select 6 1 CH4 DMA Channel 4 Interrupt CPU Select 8 1 CH5 DMA Channel 5 Interrupt CPU Select 10 1 CH6 DMA Channel 6 Interrupt CPU Select 12 1 CH7 DMA Channel 7 Interrupt CPU Select 14 1 CH8 DMA Channel 8 Interrupt CPU Select 16 1 CH9 DMA Channel 9 Interrupt CPU Select 18 1 EICCPUSEL0 EIC External Interrupts CPU Select 0 0x50 32 read-write n 0x0 0x0 EXTINT0 External Interrupt 0 CPU Select 0 1 EXTINT1 External Interrupt 1 CPU Select 2 1 EXTINT10 External Interrupt 10 CPU Select 20 1 EXTINT11 External Interrupt 11 CPU Select 22 1 EXTINT12 External Interrupt 12 CPU Select 24 1 EXTINT13 External Interrupt 13 CPU Select 26 1 EXTINT14 External Interrupt 14 CPU Select 28 1 EXTINT15 External Interrupt 15 CPU Select 30 1 EXTINT2 External Interrupt 2 CPU Select 4 1 EXTINT3 External Interrupt 3 CPU Select 6 1 EXTINT4 External Interrupt 4 CPU Select 8 1 EXTINT5 External Interrupt 5 CPU Select 10 1 EXTINT6 External Interrupt 6 CPU Select 12 1 EXTINT7 External Interrupt 7 CPU Select 14 1 EXTINT8 External Interrupt 8 CPU Select 16 1 EXTINT9 External Interrupt 9 CPU Select 18 1 EVCPUSEL0 EVSYS Channel Interrupts CPU Select 0 0x48 32 read-write n 0x0 0x0 CH0 Event Channel 0 Interrupt CPU Select 0 1 CH1 Event Channel 1 Interrupt CPU Select 2 1 CH10 Event Channel 10 Interrupt CPU Select 20 1 CH11 Event Channel 11 Interrupt CPU Select 22 1 CH2 Event Channel 2 Interrupt CPU Select 4 1 CH3 Event Channel 3 Interrupt CPU Select 6 1 CH4 Event Channel 4 Interrupt CPU Select 8 1 CH5 Event Channel 5 Interrupt CPU Select 10 1 CH6 Event Channel 6 Interrupt CPU Select 12 1 CH7 Event Channel 7 Interrupt CPU Select 14 1 CH8 Event Channel 8 Interrupt CPU Select 16 1 CH9 Event Channel 9 Interrupt CPU Select 18 1 EVCTRL Event Control 0x6 8 read-write n 0x0 0x0 BRKEI Break Input Event Enable 0 1 BRKEO Break Output Event Enable 1 1 EXTCTRL External Break Control 0x5 8 read-write n 0x0 0x0 ENABLE Enable BRK Pin 0 1 INV Invert BRK Pin 1 1 GLOBMASK Global Break Requests Mask 0xB 8 read-write n 0x0 0x0 CM0P CM0P Break Master 0 1 EVBRK Event Break Master 6 1 EXTBRK External Break Master 7 1 PPP PPP Break Master 1 1 HALT Debug Halt Request 0xC 8 write-only n 0x0 0x0 CM0P CM0P Break Master 0 1 EVBRK Event Break Master 6 1 EXTBRK External Break Master 7 1 PPP PPP Break Master 1 1 INTCPUSEL0 Interrupts CPU Select 0 0x58 32 read-write n 0x0 0x0 NVMCTRL NVMCTRL Interrupt CPU Select 8 1 RTC RTC Interrupt CPU Select 4 1 SERCOM0 SERCOM0 Interrupt CPU Select 16 1 SERCOM1 SERCOM1 Interrupt CPU Select 18 1 SERCOM2 SERCOM2 Interrupt CPU Select 20 1 SERCOM3 SERCOM3 Interrupt CPU Select 22 1 SERCOM4 SERCOM4 Interrupt CPU Select 24 1 SERCOM5 SERCOM5 Interrupt CPU Select 26 1 SYSTEM SYSTEM Interrupt CPU Select 0 1 TCC0 TCC0 Interrupt CPU Select 28 1 TCC1 TCC1 Interrupt CPU Select 30 1 USB USB Interrupt CPU Select 12 1 WDT WDT Interrupt CPU Select 2 1 INTCPUSEL1 Interrupts CPU Select 1 0x5C 32 read-write n 0x0 0x0 AC AC Interrupt CPU Select 14 1 ADC ADC Interrupt CPU Select 12 1 AES AES Interrupt CPU Select 20 1 DAC DAC Interrupt CPU Select 16 1 PICOP PICOP Interrupt CPU Select 24 1 PTC PTC Interrupt CPU Select 18 1 TC0 TC0 Interrupt CPU Select 2 1 TC1 TC1 Interrupt CPU Select 4 1 TC2 TC2 Interrupt CPU Select 6 1 TC3 TC3 Interrupt CPU Select 8 1 TC4 TC4 Interrupt CPU Select 10 1 TCC2 TCC2 Interrupt CPU Select 0 1 TRNG TRNG Interrupt CPU Select 22 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 BRK Break Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 BRK Break Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 BRK Break 0 1 INTSTATUS0 Interrupt n Status 0x40 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS1 Interrupt n Status 0x61 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS10 Interrupt n Status 0x1B7 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS11 Interrupt n Status 0x1E2 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS12 Interrupt n Status 0x20E 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS13 Interrupt n Status 0x23B 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS14 Interrupt n Status 0x269 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS15 Interrupt n Status 0x298 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS16 Interrupt n Status 0x2C8 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS17 Interrupt n Status 0x2F9 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS18 Interrupt n Status 0x32B 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS19 Interrupt n Status 0x35E 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS2 Interrupt n Status 0x83 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS20 Interrupt n Status 0x392 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS21 Interrupt n Status 0x3C7 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS22 Interrupt n Status 0x3FD 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS23 Interrupt n Status 0x434 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS24 Interrupt n Status 0x46C 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS25 Interrupt n Status 0x4A5 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS26 Interrupt n Status 0x4DF 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS27 Interrupt n Status 0x51A 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS28 Interrupt n Status 0x556 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS3 Interrupt n Status 0xA6 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS4 Interrupt n Status 0xCA 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS5 Interrupt n Status 0xEF 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS6 Interrupt n Status 0x115 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS7 Interrupt n Status 0x13C 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS8 Interrupt n Status 0x164 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS9 Interrupt n Status 0x18D 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 IRQTRIG Interrupt Trigger 0x60 16 read-write n 0x0 0x0 ENABLE Trigger Enable 0 1 IRQNUM Interrupt Request Number 1 5 OVERRIDE Interrupt Request Override Value 8 8 RESTART Debug Restart Request 0xD 8 write-only n 0x0 0x0 CM0P CM0P Break Master 0 1 EXTBRK External Break Master 7 1 PPP PPP Break Master 1 1 RSTCTRL Reset Control 0x4 8 read-write n 0x0 0x0 TC0 Basic Timer Counter 0 TC 0x0 0x0 0x40 registers n TC0 17 CC0 COUNT32 Compare and Capture 0x1C 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CC1 COUNT32 Compare and Capture 0x20 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CCBUF0 COUNT32 Compare and Capture Buffer 0x30 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 CCBUF1 COUNT32 Compare and Capture Buffer 0x34 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 COUNT COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 DRVCTRL Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 PER COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 STATUS Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare and Capture 0x38 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare and Capture 0x56 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CCBUF0 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x60 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CCBUF1 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x92 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT16 - DRVCTRL 16-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT16 - SYNCBUSY 16-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - WAVE 16-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare and Capture 0x38 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CCBUF0 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x60 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CCBUF1 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x94 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT32 - DRVCTRL 32-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT32 - SYNCBUSY 32-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT32 - WAVE 32-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare and Capture 0x38 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare and Capture 0x55 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CCBUF0 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x60 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CCBUF1 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x91 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Count 0x14 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT8 - DRVCTRL 8-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - PERBUF 8-bit Counter Mode - - COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT8 - SYNCBUSY 8-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT8 - WAVE 8-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 WAVE Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC1 Basic Timer Counter 1 TC 0x0 0x0 0x40 registers n TC1 18 CC0 COUNT32 Compare and Capture 0x1C 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CC1 COUNT32 Compare and Capture 0x20 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CCBUF0 COUNT32 Compare and Capture Buffer 0x30 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 CCBUF1 COUNT32 Compare and Capture Buffer 0x34 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 COUNT COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 DRVCTRL Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 PER COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 STATUS Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare and Capture 0x38 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare and Capture 0x56 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CCBUF0 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x60 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CCBUF1 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x92 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT16 - DRVCTRL 16-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT16 - SYNCBUSY 16-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - WAVE 16-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare and Capture 0x38 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CCBUF0 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x60 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CCBUF1 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x94 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT32 - DRVCTRL 32-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT32 - SYNCBUSY 32-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT32 - WAVE 32-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare and Capture 0x38 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare and Capture 0x55 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CCBUF0 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x60 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CCBUF1 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x91 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Count 0x14 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT8 - DRVCTRL 8-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - PERBUF 8-bit Counter Mode - - COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT8 - SYNCBUSY 8-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT8 - WAVE 8-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 WAVE Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC4 Basic Timer Counter 4 TC 0x0 0x0 0x40 registers n TC4 21 CC0 COUNT32 Compare and Capture 0x1C 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CC1 COUNT32 Compare and Capture 0x20 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CCBUF0 COUNT32 Compare and Capture Buffer 0x30 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 CCBUF1 COUNT32 Compare and Capture Buffer 0x34 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 COUNT COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 DRVCTRL Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 PER COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 STATUS Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare and Capture 0x38 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare and Capture 0x56 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CCBUF0 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x60 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CCBUF1 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x92 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT16 - DRVCTRL 16-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT16 - SYNCBUSY 16-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - WAVE 16-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare and Capture 0x38 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CCBUF0 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x60 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CCBUF1 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x94 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT32 - DRVCTRL 32-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT32 - SYNCBUSY 32-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT32 - WAVE 32-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare and Capture 0x38 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare and Capture 0x55 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CCBUF0 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x60 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CCBUF1 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x91 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Count 0x14 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT8 - DRVCTRL 8-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - PERBUF 8-bit Counter Mode - - COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT8 - SYNCBUSY 8-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT8 - WAVE 8-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 WAVE Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TCC0 Timer Counter Control 0 TCC 0x0 0x0 0x80 registers n TCC0 14 CC0 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 DITHER Dithering Cycle Number 0 6 CC1 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 DITHER Dithering Cycle Number 0 6 CC2 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 DITHER Dithering Cycle Number 0 6 CC3 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 DITHER Dithering Cycle Number 0 6 CCBUF0 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF1 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF2 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF3 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 DITHERBUF Dithering Buffer Cycle Number 0 6 COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV64 Divide by 64 0x5 DIV256 Divide by 256 0x6 DIV1024 Divide by 1024 0x7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0x0 PRESC Reload or reset counter on next prescaler clock 0x1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 0x2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0x0 DITH4 Dithering is done every 16 PWM frames 0x1 DITH5 Dithering is done every 32 PWM frames 0x2 DITH6 Dithering is done every 64 PWM frames 0x3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMA_OS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0x0 END An interrupt/event is generated when a counter cycle ends 0x1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 0x2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 0x3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0x0 RETRIGGER Start, restart or re-trigger counter on event 0x1 COUNTEV Count on event 0x2 START Start counter on event 0x3 INC Increment counter on event 0x4 COUNT Count on active state of asynchronous event 0x5 STAMP Stamp capture 0x6 FAULT Non-recoverable fault 0x7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0x0 RETRIGGER Re-trigger counter on event 0x1 DIR Direction control 0x2 STOP Stop counter on event 0x3 DEC Decrement counter on event 0x4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 0x5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 0x6 FAULT Non-recoverable fault 0x7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 PER Period 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 0 24 PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 0 24 STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only UFS Non-recoverable Update Fault State 2 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_CC0 Compare and Capture DITH4 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC1 Compare and Capture DITH4 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC2 Compare and Capture DITH4 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC3 Compare and Capture DITH4 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CCBUF0 Compare and Capture Buffer DITH4 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF1 Compare and Capture Buffer DITH4 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF2 Compare and Capture Buffer DITH4 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF3 Compare and Capture Buffer DITH4 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_COUNT Count DITH4 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 TCC_CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV64 Divide by 64 0x5 DIV256 Divide by 256 0x6 DIV1024 Divide by 1024 0x7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0x0 PRESC Reload or reset counter on next prescaler clock 0x1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 0x2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0x0 DITH4 Dithering is done every 16 PWM frames 0x1 DITH5 Dithering is done every 32 PWM frames 0x2 DITH6 Dithering is done every 64 PWM frames 0x3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 TCC_CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMA_OS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 TCC_DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 TCC_EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0x0 END An interrupt/event is generated when a counter cycle ends 0x1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 0x2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 0x3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0x0 RETRIGGER Start, restart or re-trigger counter on event 0x1 COUNTEV Count on event 0x2 START Start counter on event 0x3 INC Increment counter on event 0x4 COUNT Count on active state of asynchronous event 0x5 STAMP Stamp capture 0x6 FAULT Non-recoverable fault 0x7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0x0 RETRIGGER Re-trigger counter on event 0x1 DIR Direction control 0x2 STOP Stop counter on event 0x3 DEC Decrement counter on event 0x4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 0x5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 0x6 FAULT Non-recoverable fault 0x7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 TCC_FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 TCC_PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 TCC_PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 TCC_PER Period DITH4 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 TCC_PERBUF Period Buffer DITH4 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 TCC_STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only UFS Non-recoverable Update Fault State 2 1 TCC_SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 RAMP2C Critical RAMP2 operation 0x3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 TCC_WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 RAMP2C Critical RAMP2 operation 0x3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 TCC1 Timer Counter Control 1 TCC 0x0 0x0 0x80 registers n TCC1 15 CC0 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 DITHER Dithering Cycle Number 0 6 CC1 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 DITHER Dithering Cycle Number 0 6 CC2 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 DITHER Dithering Cycle Number 0 6 CC3 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 DITHER Dithering Cycle Number 0 6 CCBUF0 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF1 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF2 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF3 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 DITHERBUF Dithering Buffer Cycle Number 0 6 COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV64 Divide by 64 0x5 DIV256 Divide by 256 0x6 DIV1024 Divide by 1024 0x7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0x0 PRESC Reload or reset counter on next prescaler clock 0x1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 0x2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0x0 DITH4 Dithering is done every 16 PWM frames 0x1 DITH5 Dithering is done every 32 PWM frames 0x2 DITH6 Dithering is done every 64 PWM frames 0x3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMA_OS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0x0 END An interrupt/event is generated when a counter cycle ends 0x1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 0x2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 0x3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0x0 RETRIGGER Start, restart or re-trigger counter on event 0x1 COUNTEV Count on event 0x2 START Start counter on event 0x3 INC Increment counter on event 0x4 COUNT Count on active state of asynchronous event 0x5 STAMP Stamp capture 0x6 FAULT Non-recoverable fault 0x7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0x0 RETRIGGER Re-trigger counter on event 0x1 DIR Direction control 0x2 STOP Stop counter on event 0x3 DEC Decrement counter on event 0x4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 0x5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 0x6 FAULT Non-recoverable fault 0x7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 PER Period 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 0 24 PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 0 24 STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only UFS Non-recoverable Update Fault State 2 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_CC0 Compare and Capture DITH4 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC1 Compare and Capture DITH4 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC2 Compare and Capture DITH4 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC3 Compare and Capture DITH4 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CCBUF0 Compare and Capture Buffer DITH4 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF1 Compare and Capture Buffer DITH4 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF2 Compare and Capture Buffer DITH4 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF3 Compare and Capture Buffer DITH4 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_COUNT Count DITH4 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 TCC_CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV64 Divide by 64 0x5 DIV256 Divide by 256 0x6 DIV1024 Divide by 1024 0x7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0x0 PRESC Reload or reset counter on next prescaler clock 0x1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 0x2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0x0 DITH4 Dithering is done every 16 PWM frames 0x1 DITH5 Dithering is done every 32 PWM frames 0x2 DITH6 Dithering is done every 64 PWM frames 0x3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 TCC_CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMA_OS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 TCC_DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 TCC_EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0x0 END An interrupt/event is generated when a counter cycle ends 0x1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 0x2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 0x3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0x0 RETRIGGER Start, restart or re-trigger counter on event 0x1 COUNTEV Count on event 0x2 START Start counter on event 0x3 INC Increment counter on event 0x4 COUNT Count on active state of asynchronous event 0x5 STAMP Stamp capture 0x6 FAULT Non-recoverable fault 0x7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0x0 RETRIGGER Re-trigger counter on event 0x1 DIR Direction control 0x2 STOP Stop counter on event 0x3 DEC Decrement counter on event 0x4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 0x5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 0x6 FAULT Non-recoverable fault 0x7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 TCC_FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 TCC_PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 TCC_PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 TCC_PER Period DITH4 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 TCC_PERBUF Period Buffer DITH4 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 TCC_STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only UFS Non-recoverable Update Fault State 2 1 TCC_SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 RAMP2C Critical RAMP2 operation 0x3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 TCC_WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 RAMP2C Critical RAMP2 operation 0x3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 TCC2 Timer Counter Control 2 TCC 0x0 0x0 0x80 registers n TCC2 16 CC0 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 DITHER Dithering Cycle Number 0 6 CC1 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 DITHER Dithering Cycle Number 0 6 CC2 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 DITHER Dithering Cycle Number 0 6 CC3 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 DITHER Dithering Cycle Number 0 6 CCBUF0 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF1 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF2 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF3 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 DITHERBUF Dithering Buffer Cycle Number 0 6 COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV64 Divide by 64 0x5 DIV256 Divide by 256 0x6 DIV1024 Divide by 1024 0x7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0x0 PRESC Reload or reset counter on next prescaler clock 0x1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 0x2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0x0 DITH4 Dithering is done every 16 PWM frames 0x1 DITH5 Dithering is done every 32 PWM frames 0x2 DITH6 Dithering is done every 64 PWM frames 0x3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMA_OS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0x0 END An interrupt/event is generated when a counter cycle ends 0x1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 0x2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 0x3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0x0 RETRIGGER Start, restart or re-trigger counter on event 0x1 COUNTEV Count on event 0x2 START Start counter on event 0x3 INC Increment counter on event 0x4 COUNT Count on active state of asynchronous event 0x5 STAMP Stamp capture 0x6 FAULT Non-recoverable fault 0x7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0x0 RETRIGGER Re-trigger counter on event 0x1 DIR Direction control 0x2 STOP Stop counter on event 0x3 DEC Decrement counter on event 0x4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 0x5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 0x6 FAULT Non-recoverable fault 0x7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 PER Period 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 0 24 PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 0 24 STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only UFS Non-recoverable Update Fault State 2 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_CC0 Compare and Capture DITH4 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC1 Compare and Capture DITH4 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC2 Compare and Capture DITH4 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC3 Compare and Capture DITH4 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CCBUF0 Compare and Capture Buffer DITH4 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF1 Compare and Capture Buffer DITH4 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF2 Compare and Capture Buffer DITH4 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF3 Compare and Capture Buffer DITH4 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_COUNT Count DITH4 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 TCC_CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV64 Divide by 64 0x5 DIV256 Divide by 256 0x6 DIV1024 Divide by 1024 0x7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0x0 PRESC Reload or reset counter on next prescaler clock 0x1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 0x2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0x0 DITH4 Dithering is done every 16 PWM frames 0x1 DITH5 Dithering is done every 32 PWM frames 0x2 DITH6 Dithering is done every 64 PWM frames 0x3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 TCC_CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMA_OS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 TCC_DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 TCC_EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0x0 END An interrupt/event is generated when a counter cycle ends 0x1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 0x2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 0x3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0x0 RETRIGGER Start, restart or re-trigger counter on event 0x1 COUNTEV Count on event 0x2 START Start counter on event 0x3 INC Increment counter on event 0x4 COUNT Count on active state of asynchronous event 0x5 STAMP Stamp capture 0x6 FAULT Non-recoverable fault 0x7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0x0 RETRIGGER Re-trigger counter on event 0x1 DIR Direction control 0x2 STOP Stop counter on event 0x3 DEC Decrement counter on event 0x4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 0x5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 0x6 FAULT Non-recoverable fault 0x7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 TCC_FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 TCC_PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 TCC_PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 TCC_PER Period DITH4 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 TCC_PERBUF Period Buffer DITH4 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 TCC_STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only UFS Non-recoverable Update Fault State 2 1 TCC_SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 RAMP2C Critical RAMP2 operation 0x3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 TCC_WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 RAMP2C Critical RAMP2 operation 0x3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 TRNG True Random Generator TRNG 0x0 0x0 0x100 registers n TRNG 27 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 RUNSTDBY Run in Standby 6 1 DATA Output Data 0x20 32 read-only n 0x0 0x0 DATA Output Data 0 32 EVCTRL Event Control 0x4 8 read-write n 0x0 0x0 DATARDYEO Data Ready Event Output 0 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 DATARDY Data Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 DATARDY Data Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 DATARDY Data Ready Interrupt Flag 0 1 USB Universal Serial Bus USB 0x0 0x0 0x400 registers n USB 6 BINTERVAL0 HOST Bus Access Period of Pipe 0x103 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 BINTERVAL1 HOST Bus Access Period of Pipe 0x123 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 BINTERVAL2 HOST Bus Access Period of Pipe 0x143 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 BINTERVAL3 HOST Bus Access Period of Pipe 0x163 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 BINTERVAL4 HOST Bus Access Period of Pipe 0x183 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 BINTERVAL5 HOST Bus Access Period of Pipe 0x1A3 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 BINTERVAL6 HOST Bus Access Period of Pipe 0x1C3 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 BINTERVAL7 HOST Bus Access Period of Pipe 0x1E3 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE Operating Mode 7 1 MODESelect DEVICE Device Mode 0x0 HOST Host Mode 0x1 RUNSTDBY Run in Standby Mode 2 1 SWRST Software Reset 0 1 CTRLB HOST Control B 0x8 16 read-write n 0x0 0x0 AUTORESUME Auto Resume Enable 4 1 BUSRESET Send USB Reset 9 1 DETACH Detach 0 1 GNAK Global NAK 9 1 L1RESUME Send L1 Resume 11 1 LPMHDSK Link Power Management Handshake 10 2 LPMHDSKSelect NO No handshake. LPM is not supported 0x0 ACK ACK 0x1 NYET NYET 0x2 STALL STALL 0x3 NREPLY No Reply 4 1 OPMODE2 Specific Operational Mode 8 1 RESUME Send USB Resume 1 1 SOFE Start of Frame Generation Enable 8 1 SPDCONF Speed Configuration for Host 2 2 SPDCONFSelect NORMAL Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. 0x0 LS LS : Low Speed 0x1 HS HS : High Speed capable 0x2 FS Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. 0x3 HSTM HSTM: High Speed Test Mode (force high-speed mode for test mode) 0x3 TSTJ Test mode J 5 1 TSTK Test mode K 6 1 TSTPCKT Test packet mode 7 1 UPRSM Upstream Resume 1 1 VBUSOK VBUS is OK 10 1 DADD DEVICE Device Address 0xA 8 read-write n 0x0 0x0 ADDEN Device Address Enable 7 1 DADD Device Address 0 7 DESCADD Descriptor Address 0x24 32 read-write n 0x0 0x0 DESCADD Descriptor Address Value 0 32 DEVICE - CTRLA USB is Device - - Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE Operating Mode 7 1 MODESelect DEVICE Device Mode 0x0 HOST Host Mode 0x1 RUNSTDBY Run in Standby Mode 2 1 SWRST Software Reset 0 1 DEVICE - CTRLB USB is Device - - DEVICE Control B 0x8 16 read-write n 0x0 0x0 DETACH Detach 0 1 GNAK Global NAK 9 1 LPMHDSK Link Power Management Handshake 10 2 LPMHDSKSelect NO No handshake. LPM is not supported 0x0 ACK ACK 0x1 NYET NYET 0x2 STALL STALL 0x3 NREPLY No Reply 4 1 OPMODE2 Specific Operational Mode 8 1 SPDCONF Speed Configuration 2 2 SPDCONFSelect FS FS : Full Speed 0x0 LS LS : Low Speed 0x1 HS HS : High Speed capable 0x2 HSTM HSTM: High Speed Test Mode (force high-speed mode for test mode) 0x3 TSTJ Test mode J 5 1 TSTK Test mode K 6 1 TSTPCKT Test packet mode 7 1 UPRSM Upstream Resume 1 1 DEVICE - DADD USB is Device - - DEVICE Device Address 0xA 8 read-write n 0x0 0x0 ADDEN Device Address Enable 7 1 DADD Device Address 0 7 DEVICE - DESCADD USB is Device - - Descriptor Address 0x24 32 read-write n 0x0 0x0 DESCADD Descriptor Address Value 0 32 DEVICE - EPCFG0 USB is Device - - DEVICE End Point Configuration 0x200 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE - EPCFG1 USB is Device - - DEVICE End Point Configuration 0x320 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE - EPCFG2 USB is Device - - DEVICE End Point Configuration 0x460 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE - EPCFG3 USB is Device - - DEVICE End Point Configuration 0x5C0 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE - EPCFG4 USB is Device - - DEVICE End Point Configuration 0x740 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE - EPCFG5 USB is Device - - DEVICE End Point Configuration 0x8E0 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE - EPCFG6 USB is Device - - DEVICE End Point Configuration 0xAA0 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE - EPCFG7 USB is Device - - DEVICE End Point Configuration 0xC80 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE - EPINTENCLR0 USB is Device - - DEVICE End Point Interrupt Clear Flag 0x210 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE - EPINTENCLR1 USB is Device - - DEVICE End Point Interrupt Clear Flag 0x338 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE - EPINTENCLR2 USB is Device - - DEVICE End Point Interrupt Clear Flag 0x480 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE - EPINTENCLR3 USB is Device - - DEVICE End Point Interrupt Clear Flag 0x5E8 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE - EPINTENCLR4 USB is Device - - DEVICE End Point Interrupt Clear Flag 0x770 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE - EPINTENCLR5 USB is Device - - DEVICE End Point Interrupt Clear Flag 0x918 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE - EPINTENCLR6 USB is Device - - DEVICE End Point Interrupt Clear Flag 0xAE0 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE - EPINTENCLR7 USB is Device - - DEVICE End Point Interrupt Clear Flag 0xCC8 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE - EPINTENSET0 USB is Device - - DEVICE End Point Interrupt Set Flag 0x212 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE - EPINTENSET1 USB is Device - - DEVICE End Point Interrupt Set Flag 0x33B 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE - EPINTENSET2 USB is Device - - DEVICE End Point Interrupt Set Flag 0x484 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE - EPINTENSET3 USB is Device - - DEVICE End Point Interrupt Set Flag 0x5ED 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE - EPINTENSET4 USB is Device - - DEVICE End Point Interrupt Set Flag 0x776 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE - EPINTENSET5 USB is Device - - DEVICE End Point Interrupt Set Flag 0x91F 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE - EPINTENSET6 USB is Device - - DEVICE End Point Interrupt Set Flag 0xAE8 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE - EPINTENSET7 USB is Device - - DEVICE End Point Interrupt Set Flag 0xCD1 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE - EPINTFLAG0 USB is Device - - DEVICE End Point Interrupt Flag 0x20E 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE - EPINTFLAG1 USB is Device - - DEVICE End Point Interrupt Flag 0x335 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE - EPINTFLAG2 USB is Device - - DEVICE End Point Interrupt Flag 0x47C 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE - EPINTFLAG3 USB is Device - - DEVICE End Point Interrupt Flag 0x5E3 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE - EPINTFLAG4 USB is Device - - DEVICE End Point Interrupt Flag 0x76A 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE - EPINTFLAG5 USB is Device - - DEVICE End Point Interrupt Flag 0x911 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE - EPINTFLAG6 USB is Device - - DEVICE End Point Interrupt Flag 0xAD8 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE - EPINTFLAG7 USB is Device - - DEVICE End Point Interrupt Flag 0xCBF 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE - EPINTSMRY USB is Device - - DEVICE End Point Interrupt Summary 0x20 16 read-only n 0x0 0x0 EPINT0 End Point 0 Interrupt 0 1 read-only EPINT1 End Point 1 Interrupt 1 1 read-only EPINT2 End Point 2 Interrupt 2 1 read-only EPINT3 End Point 3 Interrupt 3 1 read-only EPINT4 End Point 4 Interrupt 4 1 read-only EPINT5 End Point 5 Interrupt 5 1 read-only EPINT6 End Point 6 Interrupt 6 1 read-only EPINT7 End Point 7 Interrupt 7 1 read-only DEVICE - EPSTATUS0 USB is Device - - DEVICE End Point Pipe Status 0x20C 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only DEVICE - EPSTATUS1 USB is Device - - DEVICE End Point Pipe Status 0x332 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only DEVICE - EPSTATUS2 USB is Device - - DEVICE End Point Pipe Status 0x478 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only DEVICE - EPSTATUS3 USB is Device - - DEVICE End Point Pipe Status 0x5DE 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only DEVICE - EPSTATUS4 USB is Device - - DEVICE End Point Pipe Status 0x764 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only DEVICE - EPSTATUS5 USB is Device - - DEVICE End Point Pipe Status 0x90A 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only DEVICE - EPSTATUS6 USB is Device - - DEVICE End Point Pipe Status 0xAD0 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only DEVICE - EPSTATUS7 USB is Device - - DEVICE End Point Pipe Status 0xCB6 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only DEVICE - EPSTATUSCLR0 USB is Device - - DEVICE End Point Pipe Status Clear 0x208 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Current Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only DEVICE - EPSTATUSCLR1 USB is Device - - DEVICE End Point Pipe Status Clear 0x32C 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Current Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only DEVICE - EPSTATUSCLR2 USB is Device - - DEVICE End Point Pipe Status Clear 0x470 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Current Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only DEVICE - EPSTATUSCLR3 USB is Device - - DEVICE End Point Pipe Status Clear 0x5D4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Current Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only DEVICE - EPSTATUSCLR4 USB is Device - - DEVICE End Point Pipe Status Clear 0x758 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Current Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only DEVICE - EPSTATUSCLR5 USB is Device - - DEVICE End Point Pipe Status Clear 0x8FC 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Current Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only DEVICE - EPSTATUSCLR6 USB is Device - - DEVICE End Point Pipe Status Clear 0xAC0 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Current Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only DEVICE - EPSTATUSCLR7 USB is Device - - DEVICE End Point Pipe Status Clear 0xCA4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Current Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only DEVICE - EPSTATUSSET0 USB is Device - - DEVICE End Point Pipe Status Set 0x20A 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only DEVICE - EPSTATUSSET1 USB is Device - - DEVICE End Point Pipe Status Set 0x32F 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only DEVICE - EPSTATUSSET2 USB is Device - - DEVICE End Point Pipe Status Set 0x474 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only DEVICE - EPSTATUSSET3 USB is Device - - DEVICE End Point Pipe Status Set 0x5D9 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only DEVICE - EPSTATUSSET4 USB is Device - - DEVICE End Point Pipe Status Set 0x75E 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only DEVICE - EPSTATUSSET5 USB is Device - - DEVICE End Point Pipe Status Set 0x903 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only DEVICE - EPSTATUSSET6 USB is Device - - DEVICE End Point Pipe Status Set 0xAC8 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only DEVICE - EPSTATUSSET7 USB is Device - - DEVICE End Point Pipe Status Set 0xCAD 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only DEVICE - FNUM USB is Device - - DEVICE Device Frame Number 0x10 16 read-only n 0x0 0x0 FNCERR Frame Number CRC Error 15 1 read-only FNUM Frame Number 3 11 read-only MFNUM Micro Frame Number 0 3 read-only DEVICE - FSMSTATUS USB is Device - - Finite State Machine Status 0xD 8 read-only n 0x0 0x0 FSMSTATE Fine State Machine Status 0 6 read-only FSMSTATESelect OFF OFF (L3). It corresponds to the powered-off, disconnected, and disabled state 0x1 DNRESUME DNRESUME. Down Stream Resume. 0x10 ON ON (L0). It corresponds to the Idle and Active states 0x2 UPRESUME UPRESUME. Up Stream Resume. 0x20 SUSPEND SUSPEND (L2) 0x4 RESET RESET. USB lines Reset. 0x40 SLEEP SLEEP (L1) 0x8 DEVICE - INTENCLR USB is Device - - DEVICE Device Interrupt Enable Clear 0x14 16 read-write n 0x0 0x0 EORSM End Of Resume Interrupt Enable 5 1 EORST End of Reset Interrupt Enable 3 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 RAMACER Ram Access Interrupt Enable 7 1 SOF Start Of Frame Interrupt Enable 2 1 SUSPEND Suspend Interrupt Enable 0 1 UPRSM Upstream Resume Interrupt Enable 6 1 WAKEUP Wake Up Interrupt Enable 4 1 DEVICE - INTENSET USB is Device - - DEVICE Device Interrupt Enable Set 0x18 16 read-write n 0x0 0x0 EORSM End Of Resume Interrupt Enable 5 1 EORST End of Reset Interrupt Enable 3 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 RAMACER Ram Access Interrupt Enable 7 1 SOF Start Of Frame Interrupt Enable 2 1 SUSPEND Suspend Interrupt Enable 0 1 UPRSM Upstream Resume Interrupt Enable 6 1 WAKEUP Wake Up Interrupt Enable 4 1 DEVICE - INTFLAG USB is Device - - DEVICE Device Interrupt Flag 0x1C 16 read-write n 0x0 0x0 EORSM End Of Resume 5 1 EORST End of Reset 3 1 LPMNYET Link Power Management Not Yet 8 1 LPMSUSP Link Power Management Suspend 9 1 MSOF Micro Start of Frame in High Speed Mode 1 1 RAMACER Ram Access 7 1 SOF Start Of Frame 2 1 SUSPEND Suspend 0 1 UPRSM Upstream Resume 6 1 WAKEUP Wake Up 4 1 DEVICE - PADCAL USB is Device - - USB PAD Calibration 0x28 16 read-write n 0x0 0x0 TRANSN USB Pad Transn calibration 6 5 TRANSP USB Pad Transp calibration 0 5 TRIM USB Pad Trim calibration 12 3 DEVICE - STATUS USB is Device - - DEVICE Status 0xC 8 read-only n 0x0 0x0 LINESTATE USB Line State Status 6 2 read-only LINESTATESelect 0 SE0/RESET 0x0 1 FS-J or LS-K State 0x1 2 FS-K or LS-J State 0x2 SPEED Speed Status 2 2 read-only SPEEDSelect FS Full-speed mode 0x0 HS High-speed mode 0x1 LS Low-speed mode 0x2 DEVICE - SYNCBUSY USB is Device - - Synchronization Busy 0x2 8 read-only n 0x0 0x0 ENABLE Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only EPCFG0 DEVICE End Point Configuration 0x100 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPCFG1 DEVICE End Point Configuration 0x120 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPCFG2 DEVICE End Point Configuration 0x140 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPCFG3 DEVICE End Point Configuration 0x160 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPCFG4 DEVICE End Point Configuration 0x180 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPCFG5 DEVICE End Point Configuration 0x1A0 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPCFG6 DEVICE End Point Configuration 0x1C0 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPCFG7 DEVICE End Point Configuration 0x1E0 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPINTENCLR0 DEVICE End Point Interrupt Clear Flag 0x108 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 EPINTENCLR1 DEVICE End Point Interrupt Clear Flag 0x128 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 EPINTENCLR2 DEVICE End Point Interrupt Clear Flag 0x148 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 EPINTENCLR3 DEVICE End Point Interrupt Clear Flag 0x168 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 EPINTENCLR4 DEVICE End Point Interrupt Clear Flag 0x188 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 EPINTENCLR5 DEVICE End Point Interrupt Clear Flag 0x1A8 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 EPINTENCLR6 DEVICE End Point Interrupt Clear Flag 0x1C8 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 EPINTENCLR7 DEVICE End Point Interrupt Clear Flag 0x1E8 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 EPINTENSET0 DEVICE End Point Interrupt Set Flag 0x109 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 EPINTENSET1 DEVICE End Point Interrupt Set Flag 0x129 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 EPINTENSET2 DEVICE End Point Interrupt Set Flag 0x149 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 EPINTENSET3 DEVICE End Point Interrupt Set Flag 0x169 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 EPINTENSET4 DEVICE End Point Interrupt Set Flag 0x189 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 EPINTENSET5 DEVICE End Point Interrupt Set Flag 0x1A9 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 EPINTENSET6 DEVICE End Point Interrupt Set Flag 0x1C9 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 EPINTENSET7 DEVICE End Point Interrupt Set Flag 0x1E9 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 EPINTFLAG0 DEVICE End Point Interrupt Flag 0x107 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 EPINTFLAG1 DEVICE End Point Interrupt Flag 0x127 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 EPINTFLAG2 DEVICE End Point Interrupt Flag 0x147 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 EPINTFLAG3 DEVICE End Point Interrupt Flag 0x167 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 EPINTFLAG4 DEVICE End Point Interrupt Flag 0x187 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 EPINTFLAG5 DEVICE End Point Interrupt Flag 0x1A7 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 EPINTFLAG6 DEVICE End Point Interrupt Flag 0x1C7 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 EPINTFLAG7 DEVICE End Point Interrupt Flag 0x1E7 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 EPINTSMRY DEVICE End Point Interrupt Summary 0x20 16 read-only n 0x0 0x0 EPINT0 End Point 0 Interrupt 0 1 read-only EPINT1 End Point 1 Interrupt 1 1 read-only EPINT2 End Point 2 Interrupt 2 1 read-only EPINT3 End Point 3 Interrupt 3 1 read-only EPINT4 End Point 4 Interrupt 4 1 read-only EPINT5 End Point 5 Interrupt 5 1 read-only EPINT6 End Point 6 Interrupt 6 1 read-only EPINT7 End Point 7 Interrupt 7 1 read-only EPSTATUS0 DEVICE End Point Pipe Status 0x106 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only EPSTATUS1 DEVICE End Point Pipe Status 0x126 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only EPSTATUS2 DEVICE End Point Pipe Status 0x146 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only EPSTATUS3 DEVICE End Point Pipe Status 0x166 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only EPSTATUS4 DEVICE End Point Pipe Status 0x186 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only EPSTATUS5 DEVICE End Point Pipe Status 0x1A6 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only EPSTATUS6 DEVICE End Point Pipe Status 0x1C6 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only EPSTATUS7 DEVICE End Point Pipe Status 0x1E6 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only EPSTATUSCLR0 DEVICE End Point Pipe Status Clear 0x104 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Current Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only EPSTATUSCLR1 DEVICE End Point Pipe Status Clear 0x124 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Current Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only EPSTATUSCLR2 DEVICE End Point Pipe Status Clear 0x144 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Current Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only EPSTATUSCLR3 DEVICE End Point Pipe Status Clear 0x164 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Current Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only EPSTATUSCLR4 DEVICE End Point Pipe Status Clear 0x184 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Current Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only EPSTATUSCLR5 DEVICE End Point Pipe Status Clear 0x1A4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Current Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only EPSTATUSCLR6 DEVICE End Point Pipe Status Clear 0x1C4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Current Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only EPSTATUSCLR7 DEVICE End Point Pipe Status Clear 0x1E4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Current Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only EPSTATUSSET0 DEVICE End Point Pipe Status Set 0x105 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only EPSTATUSSET1 DEVICE End Point Pipe Status Set 0x125 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only EPSTATUSSET2 DEVICE End Point Pipe Status Set 0x145 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only EPSTATUSSET3 DEVICE End Point Pipe Status Set 0x165 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only EPSTATUSSET4 DEVICE End Point Pipe Status Set 0x185 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only EPSTATUSSET5 DEVICE End Point Pipe Status Set 0x1A5 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only EPSTATUSSET6 DEVICE End Point Pipe Status Set 0x1C5 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only EPSTATUSSET7 DEVICE End Point Pipe Status Set 0x1E5 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only FLENHIGH HOST Host Frame Length 0x12 8 read-only n 0x0 0x0 FLENHIGH Frame Length 0 8 read-only FNUM HOST Host Frame Number 0x10 16 read-write n 0x0 0x0 FNCERR Frame Number CRC Error 15 1 read-only FNUM Frame Number 3 11 read-only MFNUM Micro Frame Number 0 3 read-only FSMSTATUS Finite State Machine Status 0xD 8 read-only n 0x0 0x0 FSMSTATE Fine State Machine Status 0 6 read-only FSMSTATESelect OFF OFF (L3). It corresponds to the powered-off, disconnected, and disabled state 0x1 DNRESUME DNRESUME. Down Stream Resume. 0x10 ON ON (L0). It corresponds to the Idle and Active states 0x2 UPRESUME UPRESUME. Up Stream Resume. 0x20 SUSPEND SUSPEND (L2) 0x4 RESET RESET. USB lines Reset. 0x40 SLEEP SLEEP (L1) 0x8 HOST - BINTERVAL0 USB is Host - - HOST Bus Access Period of Pipe 0x206 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 HOST - BINTERVAL1 USB is Host - - HOST Bus Access Period of Pipe 0x329 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 HOST - BINTERVAL2 USB is Host - - HOST Bus Access Period of Pipe 0x46C 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 HOST - BINTERVAL3 USB is Host - - HOST Bus Access Period of Pipe 0x5CF 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 HOST - BINTERVAL4 USB is Host - - HOST Bus Access Period of Pipe 0x752 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 HOST - BINTERVAL5 USB is Host - - HOST Bus Access Period of Pipe 0x8F5 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 HOST - BINTERVAL6 USB is Host - - HOST Bus Access Period of Pipe 0xAB8 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 HOST - BINTERVAL7 USB is Host - - HOST Bus Access Period of Pipe 0xC9B 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 HOST - CTRLA USB is Host - - Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE Operating Mode 7 1 MODESelect DEVICE Device Mode 0x0 HOST Host Mode 0x1 RUNSTDBY Run in Standby Mode 2 1 SWRST Software Reset 0 1 HOST - CTRLB USB is Host - - HOST Control B 0x8 16 read-write n 0x0 0x0 AUTORESUME Auto Resume Enable 4 1 BUSRESET Send USB Reset 9 1 L1RESUME Send L1 Resume 11 1 RESUME Send USB Resume 1 1 SOFE Start of Frame Generation Enable 8 1 SPDCONF Speed Configuration for Host 2 2 SPDCONFSelect NORMAL Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. 0x0 FS Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. 0x3 TSTJ Test mode J 5 1 TSTK Test mode K 6 1 VBUSOK VBUS is OK 10 1 HOST - DESCADD USB is Host - - Descriptor Address 0x24 32 read-write n 0x0 0x0 DESCADD Descriptor Address Value 0 32 HOST - FLENHIGH USB is Host - - HOST Host Frame Length 0x12 8 read-only n 0x0 0x0 FLENHIGH Frame Length 0 8 read-only HOST - FNUM USB is Host - - HOST Host Frame Number 0x10 16 read-write n 0x0 0x0 FNUM Frame Number 3 11 MFNUM Micro Frame Number 0 3 HOST - FSMSTATUS USB is Host - - Finite State Machine Status 0xD 8 read-only n 0x0 0x0 FSMSTATE Fine State Machine Status 0 6 read-only FSMSTATESelect OFF OFF (L3). It corresponds to the powered-off, disconnected, and disabled state 0x1 DNRESUME DNRESUME. Down Stream Resume. 0x10 ON ON (L0). It corresponds to the Idle and Active states 0x2 UPRESUME UPRESUME. Up Stream Resume. 0x20 SUSPEND SUSPEND (L2) 0x4 RESET RESET. USB lines Reset. 0x40 SLEEP SLEEP (L1) 0x8 HOST - HSOFC USB is Host - - HOST Host Start Of Frame Control 0xA 8 read-write n 0x0 0x0 FLENC Frame Length Control 0 4 FLENCE Frame Length Control Enable 7 1 HOST - INTENCLR USB is Host - - HOST Host Interrupt Enable Clear 0x14 16 read-write n 0x0 0x0 DCONN Device Connection Interrupt Disable 8 1 DDISC Device Disconnection Interrupt Disable 9 1 DNRSM DownStream to Device Interrupt Disable 5 1 HSOF Host Start Of Frame Interrupt Disable 2 1 RAMACER Ram Access Interrupt Disable 7 1 RST BUS Reset Interrupt Disable 3 1 UPRSM Upstream Resume from Device Interrupt Disable 6 1 WAKEUP Wake Up Interrupt Disable 4 1 HOST - INTENSET USB is Host - - HOST Host Interrupt Enable Set 0x18 16 read-write n 0x0 0x0 DCONN Link Power Management Interrupt Enable 8 1 DDISC Device Disconnection Interrupt Enable 9 1 DNRSM DownStream to the Device Interrupt Enable 5 1 HSOF Host Start Of Frame Interrupt Enable 2 1 RAMACER Ram Access Interrupt Enable 7 1 RST Bus Reset Interrupt Enable 3 1 UPRSM Upstream Resume fromthe device Interrupt Enable 6 1 WAKEUP Wake Up Interrupt Enable 4 1 HOST - INTFLAG USB is Host - - HOST Host Interrupt Flag 0x1C 16 read-write n 0x0 0x0 DCONN Device Connection 8 1 DDISC Device Disconnection 9 1 DNRSM Downstream 5 1 HSOF Host Start Of Frame 2 1 RAMACER Ram Access 7 1 RST Bus Reset 3 1 UPRSM Upstream Resume from the Device 6 1 WAKEUP Wake Up 4 1 HOST - PADCAL USB is Host - - USB PAD Calibration 0x28 16 read-write n 0x0 0x0 TRANSN USB Pad Transn calibration 6 5 TRANSP USB Pad Transp calibration 0 5 TRIM USB Pad Trim calibration 12 3 HOST - PCFG0 USB is Host - - HOST End Point Configuration 0x200 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST - PCFG1 USB is Host - - HOST End Point Configuration 0x320 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST - PCFG2 USB is Host - - HOST End Point Configuration 0x460 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST - PCFG3 USB is Host - - HOST End Point Configuration 0x5C0 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST - PCFG4 USB is Host - - HOST End Point Configuration 0x740 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST - PCFG5 USB is Host - - HOST End Point Configuration 0x8E0 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST - PCFG6 USB is Host - - HOST End Point Configuration 0xAA0 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST - PCFG7 USB is Host - - HOST End Point Configuration 0xC80 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST - PINTENCLR0 USB is Host - - HOST Pipe Interrupt Flag Clear 0x210 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST - PINTENCLR1 USB is Host - - HOST Pipe Interrupt Flag Clear 0x338 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST - PINTENCLR2 USB is Host - - HOST Pipe Interrupt Flag Clear 0x480 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST - PINTENCLR3 USB is Host - - HOST Pipe Interrupt Flag Clear 0x5E8 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST - PINTENCLR4 USB is Host - - HOST Pipe Interrupt Flag Clear 0x770 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST - PINTENCLR5 USB is Host - - HOST Pipe Interrupt Flag Clear 0x918 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST - PINTENCLR6 USB is Host - - HOST Pipe Interrupt Flag Clear 0xAE0 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST - PINTENCLR7 USB is Host - - HOST Pipe Interrupt Flag Clear 0xCC8 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST - PINTENSET0 USB is Host - - HOST Pipe Interrupt Flag Set 0x212 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST - PINTENSET1 USB is Host - - HOST Pipe Interrupt Flag Set 0x33B 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST - PINTENSET2 USB is Host - - HOST Pipe Interrupt Flag Set 0x484 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST - PINTENSET3 USB is Host - - HOST Pipe Interrupt Flag Set 0x5ED 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST - PINTENSET4 USB is Host - - HOST Pipe Interrupt Flag Set 0x776 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST - PINTENSET5 USB is Host - - HOST Pipe Interrupt Flag Set 0x91F 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST - PINTENSET6 USB is Host - - HOST Pipe Interrupt Flag Set 0xAE8 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST - PINTENSET7 USB is Host - - HOST Pipe Interrupt Flag Set 0xCD1 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST - PINTFLAG0 USB is Host - - HOST Pipe Interrupt Flag 0x20E 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST - PINTFLAG1 USB is Host - - HOST Pipe Interrupt Flag 0x335 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST - PINTFLAG2 USB is Host - - HOST Pipe Interrupt Flag 0x47C 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST - PINTFLAG3 USB is Host - - HOST Pipe Interrupt Flag 0x5E3 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST - PINTFLAG4 USB is Host - - HOST Pipe Interrupt Flag 0x76A 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST - PINTFLAG5 USB is Host - - HOST Pipe Interrupt Flag 0x911 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST - PINTFLAG6 USB is Host - - HOST Pipe Interrupt Flag 0xAD8 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST - PINTFLAG7 USB is Host - - HOST Pipe Interrupt Flag 0xCBF 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST - PINTSMRY USB is Host - - HOST Pipe Interrupt Summary 0x20 16 read-only n 0x0 0x0 EPINT0 Pipe 0 Interrupt 0 1 read-only EPINT1 Pipe 1 Interrupt 1 1 read-only EPINT2 Pipe 2 Interrupt 2 1 read-only EPINT3 Pipe 3 Interrupt 3 1 read-only EPINT4 Pipe 4 Interrupt 4 1 read-only EPINT5 Pipe 5 Interrupt 5 1 read-only EPINT6 Pipe 6 Interrupt 6 1 read-only EPINT7 Pipe 7 Interrupt 7 1 read-only HOST - PSTATUS0 USB is Host - - HOST End Point Pipe Status 0x20C 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only HOST - PSTATUS1 USB is Host - - HOST End Point Pipe Status 0x332 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only HOST - PSTATUS2 USB is Host - - HOST End Point Pipe Status 0x478 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only HOST - PSTATUS3 USB is Host - - HOST End Point Pipe Status 0x5DE 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only HOST - PSTATUS4 USB is Host - - HOST End Point Pipe Status 0x764 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only HOST - PSTATUS5 USB is Host - - HOST End Point Pipe Status 0x90A 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only HOST - PSTATUS6 USB is Host - - HOST End Point Pipe Status 0xAD0 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only HOST - PSTATUS7 USB is Host - - HOST End Point Pipe Status 0xCB6 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only HOST - PSTATUSCLR0 USB is Host - - HOST End Point Pipe Status Clear 0x208 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only HOST - PSTATUSCLR1 USB is Host - - HOST End Point Pipe Status Clear 0x32C 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only HOST - PSTATUSCLR2 USB is Host - - HOST End Point Pipe Status Clear 0x470 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only HOST - PSTATUSCLR3 USB is Host - - HOST End Point Pipe Status Clear 0x5D4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only HOST - PSTATUSCLR4 USB is Host - - HOST End Point Pipe Status Clear 0x758 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only HOST - PSTATUSCLR5 USB is Host - - HOST End Point Pipe Status Clear 0x8FC 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only HOST - PSTATUSCLR6 USB is Host - - HOST End Point Pipe Status Clear 0xAC0 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only HOST - PSTATUSCLR7 USB is Host - - HOST End Point Pipe Status Clear 0xCA4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only HOST - PSTATUSSET0 USB is Host - - HOST End Point Pipe Status Set 0x20A 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only HOST - PSTATUSSET1 USB is Host - - HOST End Point Pipe Status Set 0x32F 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only HOST - PSTATUSSET2 USB is Host - - HOST End Point Pipe Status Set 0x474 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only HOST - PSTATUSSET3 USB is Host - - HOST End Point Pipe Status Set 0x5D9 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only HOST - PSTATUSSET4 USB is Host - - HOST End Point Pipe Status Set 0x75E 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only HOST - PSTATUSSET5 USB is Host - - HOST End Point Pipe Status Set 0x903 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only HOST - PSTATUSSET6 USB is Host - - HOST End Point Pipe Status Set 0xAC8 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only HOST - PSTATUSSET7 USB is Host - - HOST End Point Pipe Status Set 0xCAD 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only HOST - STATUS USB is Host - - HOST Status 0xC 8 read-write n 0x0 0x0 LINESTATE USB Line State Status 6 2 read-only SPEED Speed Status 2 2 HOST - SYNCBUSY USB is Host - - Synchronization Busy 0x2 8 read-only n 0x0 0x0 ENABLE Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only HSOFC HOST Host Start Of Frame Control 0xA 8 read-write n 0x0 0x0 FLENC Frame Length Control 0 4 FLENCE Frame Length Control Enable 7 1 INTENCLR HOST Host Interrupt Enable Clear 0x14 16 read-write n 0x0 0x0 DCONN Device Connection Interrupt Disable 8 1 DDISC Device Disconnection Interrupt Disable 9 1 DNRSM DownStream to Device Interrupt Disable 5 1 EORSM End Of Resume Interrupt Enable 5 1 EORST End of Reset Interrupt Enable 3 1 HSOF Host Start Of Frame Interrupt Disable 2 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 RAMACER Ram Access Interrupt Disable 7 1 RST BUS Reset Interrupt Disable 3 1 SOF Start Of Frame Interrupt Enable 2 1 SUSPEND Suspend Interrupt Enable 0 1 UPRSM Upstream Resume from Device Interrupt Disable 6 1 WAKEUP Wake Up Interrupt Disable 4 1 INTENSET HOST Host Interrupt Enable Set 0x18 16 read-write n 0x0 0x0 DCONN Link Power Management Interrupt Enable 8 1 DDISC Device Disconnection Interrupt Enable 9 1 DNRSM DownStream to the Device Interrupt Enable 5 1 EORSM End Of Resume Interrupt Enable 5 1 EORST End of Reset Interrupt Enable 3 1 HSOF Host Start Of Frame Interrupt Enable 2 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 RAMACER Ram Access Interrupt Enable 7 1 RST Bus Reset Interrupt Enable 3 1 SOF Start Of Frame Interrupt Enable 2 1 SUSPEND Suspend Interrupt Enable 0 1 UPRSM Upstream Resume fromthe device Interrupt Enable 6 1 WAKEUP Wake Up Interrupt Enable 4 1 INTFLAG HOST Host Interrupt Flag 0x1C 16 read-write n 0x0 0x0 DCONN Device Connection 8 1 DDISC Device Disconnection 9 1 DNRSM Downstream 5 1 EORSM End Of Resume 5 1 EORST End of Reset 3 1 HSOF Host Start Of Frame 2 1 LPMNYET Link Power Management Not Yet 8 1 LPMSUSP Link Power Management Suspend 9 1 MSOF Micro Start of Frame in High Speed Mode 1 1 RAMACER Ram Access 7 1 RST Bus Reset 3 1 SOF Start Of Frame 2 1 SUSPEND Suspend 0 1 UPRSM Upstream Resume from the Device 6 1 WAKEUP Wake Up 4 1 PADCAL USB PAD Calibration 0x28 16 read-write n 0x0 0x0 TRANSN USB Pad Transn calibration 6 5 TRANSP USB Pad Transp calibration 0 5 TRIM USB Pad Trim calibration 12 3 PCFG0 HOST End Point Configuration 0x100 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 PCFG1 HOST End Point Configuration 0x120 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 PCFG2 HOST End Point Configuration 0x140 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 PCFG3 HOST End Point Configuration 0x160 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 PCFG4 HOST End Point Configuration 0x180 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 PCFG5 HOST End Point Configuration 0x1A0 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 PCFG6 HOST End Point Configuration 0x1C0 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 PCFG7 HOST End Point Configuration 0x1E0 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 PINTENCLR0 HOST Pipe Interrupt Flag Clear 0x108 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 PINTENCLR1 HOST Pipe Interrupt Flag Clear 0x128 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 PINTENCLR2 HOST Pipe Interrupt Flag Clear 0x148 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 PINTENCLR3 HOST Pipe Interrupt Flag Clear 0x168 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 PINTENCLR4 HOST Pipe Interrupt Flag Clear 0x188 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 PINTENCLR5 HOST Pipe Interrupt Flag Clear 0x1A8 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 PINTENCLR6 HOST Pipe Interrupt Flag Clear 0x1C8 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 PINTENCLR7 HOST Pipe Interrupt Flag Clear 0x1E8 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 PINTENSET0 HOST Pipe Interrupt Flag Set 0x109 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 PINTENSET1 HOST Pipe Interrupt Flag Set 0x129 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 PINTENSET2 HOST Pipe Interrupt Flag Set 0x149 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 PINTENSET3 HOST Pipe Interrupt Flag Set 0x169 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 PINTENSET4 HOST Pipe Interrupt Flag Set 0x189 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 PINTENSET5 HOST Pipe Interrupt Flag Set 0x1A9 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 PINTENSET6 HOST Pipe Interrupt Flag Set 0x1C9 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 PINTENSET7 HOST Pipe Interrupt Flag Set 0x1E9 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 PINTFLAG0 HOST Pipe Interrupt Flag 0x107 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 PINTFLAG1 HOST Pipe Interrupt Flag 0x127 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 PINTFLAG2 HOST Pipe Interrupt Flag 0x147 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 PINTFLAG3 HOST Pipe Interrupt Flag 0x167 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 PINTFLAG4 HOST Pipe Interrupt Flag 0x187 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 PINTFLAG5 HOST Pipe Interrupt Flag 0x1A7 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 PINTFLAG6 HOST Pipe Interrupt Flag 0x1C7 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 PINTFLAG7 HOST Pipe Interrupt Flag 0x1E7 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 PINTSMRY HOST Pipe Interrupt Summary 0x20 16 read-only n 0x0 0x0 EPINT0 Pipe 0 Interrupt 0 1 read-only EPINT1 Pipe 1 Interrupt 1 1 read-only EPINT2 Pipe 2 Interrupt 2 1 read-only EPINT3 Pipe 3 Interrupt 3 1 read-only EPINT4 Pipe 4 Interrupt 4 1 read-only EPINT5 Pipe 5 Interrupt 5 1 read-only EPINT6 Pipe 6 Interrupt 6 1 read-only EPINT7 Pipe 7 Interrupt 7 1 read-only PSTATUS0 HOST End Point Pipe Status 0x106 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only PSTATUS1 HOST End Point Pipe Status 0x126 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only PSTATUS2 HOST End Point Pipe Status 0x146 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only PSTATUS3 HOST End Point Pipe Status 0x166 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only PSTATUS4 HOST End Point Pipe Status 0x186 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only PSTATUS5 HOST End Point Pipe Status 0x1A6 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only PSTATUS6 HOST End Point Pipe Status 0x1C6 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only PSTATUS7 HOST End Point Pipe Status 0x1E6 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only PSTATUSCLR0 HOST End Point Pipe Status Clear 0x104 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only PSTATUSCLR1 HOST End Point Pipe Status Clear 0x124 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only PSTATUSCLR2 HOST End Point Pipe Status Clear 0x144 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only PSTATUSCLR3 HOST End Point Pipe Status Clear 0x164 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only PSTATUSCLR4 HOST End Point Pipe Status Clear 0x184 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only PSTATUSCLR5 HOST End Point Pipe Status Clear 0x1A4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only PSTATUSCLR6 HOST End Point Pipe Status Clear 0x1C4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only PSTATUSCLR7 HOST End Point Pipe Status Clear 0x1E4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only PSTATUSSET0 HOST End Point Pipe Status Set 0x105 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only PSTATUSSET1 HOST End Point Pipe Status Set 0x125 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only PSTATUSSET2 HOST End Point Pipe Status Set 0x145 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only PSTATUSSET3 HOST End Point Pipe Status Set 0x165 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only PSTATUSSET4 HOST End Point Pipe Status Set 0x185 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only PSTATUSSET5 HOST End Point Pipe Status Set 0x1A5 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only PSTATUSSET6 HOST End Point Pipe Status Set 0x1C5 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only PSTATUSSET7 HOST End Point Pipe Status Set 0x1E5 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only STATUS HOST Status 0xC 8 read-write n 0x0 0x0 LINESTATE USB Line State Status 6 2 read-only LINESTATESelect 0 SE0/RESET 0x0 1 FS-J or LS-K State 0x1 2 FS-K or LS-J State 0x2 SPEED Speed Status 2 2 read-only SPEEDSelect FS Full-speed mode 0x0 HS High-speed mode 0x1 LS Low-speed mode 0x2 SYNCBUSY Synchronization Busy 0x2 8 read-only n 0x0 0x0 ENABLE Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only WDT Watchdog Timer WDT 0x0 0x0 0x10 registers n WDT 1 CLEAR Clear 0xC 8 write-only n 0x0 0x0 CLEAR Watchdog Clear 0 8 write-only CLEARSelect KEY Clear Key 0xa5 CONFIG Configuration 0x1 8 read-write n 0x0 0x0 PER Time-Out Period 0 4 PERSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xa CYC16384 16384 clock cycles 0xb WINDOW Window Mode Time-Out Period 4 4 WINDOWSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xa CYC16384 16384 clock cycles 0xb CTRLA Control 0x0 8 read-write n 0x0 0x0 ALWAYSON Always-On 7 1 ENABLE Enable 1 1 WEN Watchdog Timer Window Mode Enable 2 1 EWCTRL Early Warning Interrupt Control 0x2 8 read-write n 0x0 0x0 EWOFFSET Early Warning Interrupt Time Offset 0 4 EWOFFSETSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xa CYC16384 16384 clock cycles 0xb INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 EW Early Warning Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 EW Early Warning Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 EW Early Warning 0 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 ALWAYSON Always-On Busy 3 1 read-only CLEAR Clear Busy 4 1 read-only ENABLE Enable Busy 1 1 read-only WEN Window Enable Busy 2 1 read-only